Trace signal selection to enhance timing and logic visibility in post-silicon validation

Abstract

Abstract-Trace buffer technology allows tracking the values of a few number of state elements inside a chip within a desired time window,which is used to analyze logic errors during post-silicon validation. Due to limitation in the bandwidth of trace buffers, only few state elements can be selected for tracing. In this work we first propose two improvements to existing "signal selection" algorithms to further increase the logic restorability inside the chip. In addition, we observe that different selections of trace signals can result in the same quality, measured as a logic visibility metric. Based on this observation, we propose a procedure which biases the selection to increase the restorability of a desired set of critical state elements, without sacrificing the (overall) logic visibility. We propose to select the critical state elements to increase the "timing visibility" inside the chip to facilitate the debugging of timing errors which are perhaps the most challenging type of error to debug at the post-silicon stage. Specifically, we introduce a case when the critical state elements are selected to track the transient fluctuations in the power delivery network which can cause significant variations in the delays of the speedpaths in the circuit in nanometer technologies. This paper proposes to use the trace buffer technology to increase the timing visibility inside the chip, without sacrificing the logic visibility. I. INTRODUCTIONPost-silicon validation of VLSI chips has become significantly time-consuming in nanometer technologies and impacting the product time-to-market. Due to the high complexity of modern day electronic systems, logic bugs may escape the pre-silicon validation stage. However, at this stage, the lack of visibility to the signals inside the chip makes the validation a cumbersome task.Trace buffer technology has been recently used in order to track few internal state elements (i.e., signals) during the operation of a chip. These signals are selected for tracing at the design stage and the traces are analyzed at the post-silicon stage to debug logic errors. Many recent works have focused on the trace selection problem in order to maximize the chip logic visibility [4], [5], [6], where visibility is the metric used to reflect the degree of restoring the remaining state elements in the chip using the selected trace signals.In this work, we first present two enhancements to the existing trace selection algorithms:1. During computation of the visibility corresponding to a set of candidate trace signals, we show the ordering of state elements is very important. We discuss an ordering which results in more accurate computation of visibility during trace selection. 2. We propose a Pareto-algebriac procedure which in effect defers the selection of multiple trace signals, compared to existing greedy techniques which select one trace at each step. As a result, we can obtain a solution of higher visibility. Furthermore, we observe that due to the limited bandwidth of the trace buffer, many alternat...

Simulation-based signal selection for state restoration in silicon debug

“…Another line of research [12], [13] suggests that not all state elements or signals are equally relevant for debugging purposes. Hence, instead of striving to maximize the state restoration ratio, the authors of those works focus on maximizing restorability of a specified subset of signals, while minimizing the impact to other flip-flops.…”

“…Hence, instead of striving to maximize the state restoration ratio, the authors of those works focus on maximizing restorability of a specified subset of signals, while minimizing the impact to other flip-flops. In particular, the algorithm in [13] uses a probabilistic estimation metric analogous to [8], and follows a pareto optimal selection process. We show that our solution can be adapted to solve this problem variant as well, by simply assigning larger weight coefficients to the set of critical flip-flops.…”

“…Adapting to Biased Selection: An important variation of the problem of state restoration was addressed in [13]. A set of critical flip-flops (SC ) are identified among the entire set of flip-flops (S all ) based on a user-defined criteria.…”

“…A set of critical flip-flops (SC ) are identified among the entire set of flip-flops (S all ) based on a user-defined criteria. For example in [13], the objective is to estimate power droop in the circuit, hence the netlist is partitioned into a coarse placement grid, and one flip-flop is selected from each grid block as a critical flip-flop. The trace selection algorithm biases the selection process so to restore the maximum number of critical flip-flops, while sacrificing restoration for non-critical flip-flops the least.…”

On efficient silicon debug with flexible trace interconnection fabric

“…Many solutions have been proposed in the literature to tackle this problem [17][18][19][20][21][22][23][24]. On the other hand, due to the limited trace bandwidth, we are not able to trace all the tapped signals concurrently in each debug run.…”