Trace Theory and VLSJ Design

Snepscheut, Jan L. A. van de

doi:10.1007/bfb0031414

Cited by 77 publications

(31 citation statements)

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“…In 1985, Van de Sneupschet observed that the decreasing feature size of very large scale integration devices would have lead to "a decrease of the propagation speed of electrical signals relative to the switching speed," and proposed the use of suitable communication protocols to obtain chip designs whose correct operation is independent of the propagation speed [30]. This work has more than one contact point with the present paper, but differs on the basic fact that leads to the choice of speed-independent circuits over synchronous circuits.…”

Section: Background and Related Workmentioning

confidence: 99%

Theory of latency-insensitive design

Carloni

McMillan

Sangiovanni-Vincentelli

2001

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

344

245

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Abstract-The theory of latency-insensitive design is presented as the foundation of a new correct-by-construction methodology to design complex systems by assembling intellectual property components. Latency-insensitive designs are synchronous distributed systems and are realized by composing functional modules that exchange data on communication channels according to an appropriate protocol. The protocol works on the assumption that the modules are stallable, a weak condition to ask them to obey. The goal of the protocol is to guarantee that latency-insensitive designs composed of functionally correct modules behave correctly independently of the channel latencies. This allows us to increase the robustness of a design implementation because any delay variations of a channel can be "recovered" by changing the channel latency while the overall system functionality remains unaffected. As a consequence, an important application of the proposed theory is represented by the latency-insensitive methodology to design large digital integrated circuits by using deep submicrometer technologies.Index Terms-Deep submicrometer design, formal methods, latency-insensitive protocols, system design.

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Section: Background and Related Workmentioning

confidence: 99%

Theory of latency-insensitive design

Carloni

McMillan

Sangiovanni-Vincentelli

2001

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

344

245

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“…Moreover, trace theories are used to describe the semantics of data flow networks (see Kahn [18], Brock & Ackerman [10]) and the semantics of restoring circuit logic (see Ebergen [13], Rem [27] and Van de Snepscheut [29]. Restoring circuit logic is intended to describe the behaviour of circuits regardless of delays in the connecting wires.…”

Section: Interpreted In Asccsmentioning

confidence: 99%

Process algebra with asynchronous communication mechanisms

Bergstra¹,

Klop²,

Tucker

1985

Lecture Notes in Computer Science

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“…Our work is mainly focussed at the signal-level, comparable to the level being explored by current Signal transition graph and State graph based methods [2,4,10,11,20,21,22]. Trace theory has been developed by Rem, van de Snepscheut, and Udding [16,19], and by Dill [6] for the analysis and verification of speed-independent circuits. In contrast to these works, our work here is focussed on automated synthesis and hierarchical optimization.…”

Section: Introductionmentioning

confidence: 99%

Hierarchical Optimization of Asynchronous Circuits

Lin¹

1995

32nd Design Automation Conference

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-Many asynchronous designs are naturally specified and implemented hierarchically as an interconnection of separate asynchronous modules that operate concurrently and communicate with each other. This paper is concerned with the problem of synthesizing such hierarchically defined systems. When the individual components are synthesized and implemented separately, it is desirable to take into account the degrees of freedom that arise from the interactions with the other components and from the specification. Specifically, we consider how one can find the set of implementations that can be "correctly substituted" for a component in the system while preserving the behavior of the total system. The notion of correct substitution is formally defined for a hierarchical network of possibly non-deterministic modules and a new solution framework based on trace theory is presented to compute and represent this complete set of correct substitutions. We show that the complete set can be captured by a single trace structure using the notion of a "maximal trace structure". We indicate how asynchronous synthesis methods may be applied to explore the solution space e.g. to generate a delay-insensitive implementation. I INTRODUCTIONThe role of asynchronous design is gaining importance due to increasing difficulties with problems like clock skew and power dissipation. In many design scenarios, the design is most naturally described and implemented hierarchically as a network of separate asynchronous modules that operate concurrently and communicate with each other. Hierarchical representations are especially important when the design is compiled from a highlevel language. Also, implementation constraints may force their physical implementations to be separated. Indeed, real-life designs show that many asynchronous applications are inherently distributive and highly interactive, thus requiring methods to handle them. When optimizing each individual component separately, it is desirable to take into account the degrees of freedom that arise from the interactions with the other components and from the specification. This is analogous to the problem of optimizing hierarchically combinational and synchronous circuits, which has been studied extensively.For the design of asynchronous control circuits, the existing literature describes a number of automated algorithmic approaches based on Petri net and state machine models [2,4,10,11,15,20,21,22,23]. These works have focussed mainly on the synthesis and optimization of individual asynchronous modules without considering the optimization freedom available in optimizing concurrent behavior. Methods based on models of communicating processes have also been extensively studied in the literature [1,3,13,18]. These methods are mainly based on syntax-directed translation techniques. Though these methods can effectively model concurrent behavior, they also have This research was sponsored in part by the European Commission under the ESPRIT (6143) project "EXACT" and HCM contract ERBCHBG...

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Trace Theory and VLSJ Design

Cited by 77 publications

References 0 publications

Theory of latency-insensitive design

Theory of latency-insensitive design

Process algebra with asynchronous communication mechanisms

Hierarchical Optimization of Asynchronous Circuits

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