Track-Assignment Detailed Routing Using Attention-based Policy Model With Supervision

Abstract

Detailed routing is one of the most critical steps in analog circuit design. Complete routing has become increasingly more challenging in advanced node analog circuits, making advances in efficient automatic routers ever more necessary. In this work, we propose a machine learning driven method for solving the track-assignment detailed routing problem for advanced node analog circuits. Our approach adopts an attention-based reinforcement learning (RL) policy model. Our main insight and advancement over this RL model is the use of supervision as a way to leverage solutions generated by a conventional genetic algorithm (GA). For this, our approach minimizes the Kullback-Leibler divergence loss between the output from the RL policy model and a solution distribution obtained from the genetic solver. The key advantage of this approach is that the router can learn a policy in an offline setting with supervision, while improving the run-time performance nearly 100× over the genetic solver. Moreover, the quality of the solutions our approach produces matches well with those generated by GA. We show that especially for complex problems, our supervised RL method provides good quality solution similar to conventional attention-based RL without comprising run time performance. The ability to learn from example designs and train the router to get similar solutions with orders of magnitude run-time improvement can impact the design flow dramatically, potentially enabling increased design exploration and routability-driven placement.

Analog Integrated Circuit Routing Techniques: An Extensive Review

“…The algorithm is designed to encode the design rules into the track-assignment steps, and the model determines the best sequence of the set of device pairs to be routed, such that the overall solution quality is maximized. In [168], the training of the reinforced learning model was supervised with past solutions, leveraging the information previously produced. Both methods provide nearly 100× runtime speed-ups when comparing with a plain schedular based on an EA, while generating solutions that are comparable in quality.…”

FanoutNet: A Neuralized PCB Fanout Automation Method Using Deep Reinforcement Learning

“…Recent years, deep learning based EDA routing method has been widely concerned by the industrial and academic community. For integrated circuits (IC) routing, some deep reinforcement learning methods have been presented for global routing (Liao et al 2020b), detail routing (Lin et al 2021c), and track assignment (Liao et al 2020a). Deep reinforcement learning has also been shown to solve some fundamental problems, including rectilinear Steiner minimum tree problem (Liu, Chen, and Young 2021) and travelling salesman problem (Kool, Van Hoof, and Welling 2018).…”

Collaborative Distillation Meta Learning for Simulation Intensive Hardware Design

“…Probability calculations using h (c) , and h i , i ∈ {1, ..., N × M } in (11)(12)(13)(14) are exactly identical to (5)(6)(7)(8) in [19] except the masking mechanism in equation 13 and equation 14. Because [19] solves TSP, so they mask the previously selected actions by forcing −∞ as compatibility u (c)j .…”

“…Many studies have already shown that deep reinforcement learning (DRL), one of the representative ML method for sequential decision making, is applicable to various tasks in modern chip design; chip placement [2,3], routing [4,5], circuit design [6], logic synthesis [7,8] and bi-level hardware optimization [9]. However, most DRL-based hardware design methods used simplified objectives.…”

“…However, most DRL-based hardware design methods used simplified objectives. For example, DRL-based placement and routing works [2,4,5] took wire-length and congestion as objectives for fast computations, instead of actual electrical performance.…”