Tradeoff of DC/RF performance versus reliability in 0.1 μm InP HEMTs

Abstract

The tradeoff of DCBF performance versus reliability has been explored on 0.1 pm InP HEMTs. The tradeoff between performance and reliability shows the dependence on the process techniques.While higher performance could be achieved with certain process techniques, the reliability performance is adversely affected. Nevertheless, all the process variations explored here exhibit activation energy of approximately 1.9 eV. However, the time-to-failure (TTF) at lifetest temperatures of 230°C and 250°C and median-time-to-failure (MTTF) at junction temperature of 125°C depend on the process techniques. The resuits are beneficial for balancing performance versus reliability through the adjustment of the processing technique. I. IntroductiodInGaAsiInAIAdInP microwave monolithic integrated circuits (MMICs) with high electron mobility transistors (HEMTs) have demonstrated supenor microwave and millimeter wave performance at 44 GHz [I], 94 GHz [Z-31, 118 GHz F4-51, 155 GHz [6], and 183 GHz [7-8]. The further qualification of InGaAslInAIAshP MMIC technology in the categories of hgh-temperature reliability, Gammdneutron dose radiation, RF survivability, electrostatic discharge (ESD) test, and hydrogen rcliability demonstrates the readiness of InGaAs/lnAlAs/lrP MMIC technology for the spaceimilitary applications in Northrop G " a n Space Technology [9]. Moreover, high reliability performance has been demonstrated on 0.07 prn InP HEMT MMICs [lo] and metamorphic HEMTs (MHEMTs) [I 1, 121, While MMICs with excellent RF performance have been demonstrated, they might not exhibit the best reIiability pcrformance. Accordingly, it is essential to understand the correlation of DC/RF performance with reliability in InP HEMTs. In 1997, Y. C. Chcn et. al. [13] studied the effect of recess optimization on the power performance in InP HEMT power amplifiers. It was observed that there is tradeoff between targeted recess depth and DC/power performance. Nevertheless, there is no available information on the effect of recess depth variation on reliability performance. Recently, Menozzi et. al. [ 141 reported thc effect of gate recess time on hot electron reliability. In his investigation, devices were stressed at room temperature. It was found that lhe hot electron reliability or wide-recess devices is inferior to that of devices with narrow recess. The result was attributed to the semiconductor-SiN interface being closer to the channel on the 0-7803-8595-0/oQ/S20.00 02004 FEEE wide-recess devices. Therefore, the screening provided by the high-doping capping layer is reduced [ 141. NevertheIess, the effect of gate recess time on high-temperature reliability was lacking. Recently, M . Dammann et. al. Ell] reported that the median lifetime of enhancement MHEMTs (MTTF =I. 1 xl O6 hours) is approximately one order of magnitude smaller as compared t o depletion MHEMTs (MTTF =3x107 hours). Thefaster degradation of enhancement MHEMTs as compared to depletion MHEMTs was attributed to smaller gate to channel distance andor the smaller recess length, leading ...

Progressive Schottky junction reaction induced degradation in Pt-sunken gate InP HEMT MMICs for high reliability applications

“…A recent investigation of InP HEMTs degradation using a scanning-transmission-electronmicroscope (STEM) technique [26] reveals the physical evidence of Ti-InAlAs reaction in InP HEMTs under the elevated temperature lifetest. Although the high activation energy (Ea) was reported in InP HEMTs with the gate metal stacks of Ti/Pt/Au [20,30], the degree of reaction between the gate metal stacks of Ti/Pt/Au and the InAlAs Schottky barrier layer strongly depends on the InAlAs surface conditions prior to the Ti/Pt/Au gate metal deposition. The variations of the InAlAs surface conditions could be induced by either gate recess wet etching and/or process-related dry etching.…”

“…Several degradation causes in InP HEMTs were reported in literature [16,[21][22][23][24][25][26][27][28][29][30], however, most of them were eliminated due to the maturity of manufacturing processes and HEMT epitaxial materials. Nevertheless, gate metal reaction with the InAlAs material in InP HEMTs subjected to elevated temperature lifetest was still observed to be the primary degradation mechanism.…”

“…The variations of reliability performance were mainly attributed to different degradation mechanisms, consisting of fluorine contamination [23], ohmic contact degradation [16], gate metal stacks [24][25][26], layer structure [27], bias dependence [28], the variation of gate recess depth [29][30], and gate metal sinking [21][22]. It was observed that the degradation mechanisms strongly depend on the process techniques employed in a particular InAlAs/InGaAs/InP HEMT technology, therefore causing the distinct reliability performance from company to company.…”