Transformation-Based Verification Using Generalized Retiming

Abstract

In this paper we present the application of generalized retiming for temporal property checking. Retiming is a structural transformation that relocates registers in a circuit-based design representation without changing its actual input-output behavior. We discuss the application of retiming to minimize the number of registers with the goal of increasing the capacity of symbolic state traversal. In particular, we demonstrate that the classical definition of retiming can be generalized for verification by relaxing the notion of design equivalence and physical implementability. This includes (1) omitting the need for equivalent reset states by using an initialization stump, (2) supporting negative registers, handled by a general functional relation to future time frames, and (3) eliminating peripheral registers by converting them into simple temporal offsets. The presented results demonstrate that the application of retiming in verification can significantly increase the capacity of symbolic state traversal. Our experiments also demonstrate that the repeated use of retiming interleaved with other structural simplifications can yield reductions beyond those possible with single applications of the individual approaches. This result suggests that a tool architecture based on re-entrant transformation engines can potentially decompose and solve verification problems that otherwise would be infeasible.

Speculative reduction-based scalable redundancy identification

“…For SYNTH3, the application of phase abstraction MOD [21] followed by min-area retiming RET [13] and combinational optimization COM [12] on the speculatively-reduced netlist is able to efficiently solve all miters. For IOC, MOD and COM followed by structural isomorphism detection ISO dramatically simplifies the speculatively-reduced netlist.…”

“…Experiments confirm that transformation and verification algorithms are much more effective after the speculative merging. For example, speculative merging helps share logic across the netlist comprising two designs being equivalence checked, in turn enabling sharing-aware logic rewriting algorithms [12] and min-area retiming [13] to further reduce the speculatively-reduced netlist in ways that would not be possible otherwise. Speculative merging can also increase the capability of structural isomorphism detection [14] to suppress isomorphic miters.…”

Exploiting refactoring in formal verification

“…Kuehlmann1 et al [10] have developed an approach called transformation-based verification for sequential verification of circuit-based designs. The approach uses structural transformation that relocates registers in a circuit-based design representation without changing its actual input-output behavior, to increase the capacity of symbolic state traversal.…”

On the verification of sequential equivalence

“…However, these formal methods cannot be scaled as easily with the increasing complexity of system designs due to the state explosion problem, which says that the state space grows exponentially in the number of state variables. Therefore recent research [3], [11] has focused on reducing the number of state variables by retiming [13], with the hope that verification can be conducted on the reduced circuits. Unlike these circuit-based transformations, this paper reduces the register count in the verification construction.…”