Transformation of systolic algorithms for interleaving partitions

Fernandez, A.; Llaberia, J.M.; Navarro, Juan J.; Valero-García, Miguel

doi:10.1109/asap.1991.238893

Cited by 3 publications

(2 citation statements)

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“…The potential given by interleaving is exploited also in Digital Signal Processors (DSP); in [18] and [49] a system level solution starting from the algorithm and taking into account programmability of DSP is analyzed. Some works have been presented to transform algorithms to exploit interleaving: in [19] a method that selects and transforms a systolic algorithm into a parallel algorithm with high granularity is presented; this method returns the exact code to run on each processing element of the multicomputer system.…”

Section: A Systematic Methods To Exploit Sa: Interleavingmentioning

confidence: 99%

“…With a principle similar to interleaving in processors out-of-order execution and, especially, to interleaved multithreading in modern CPUs, by accurately organizing input data delivery, SAs performance can be dramatically improved. Even though this approach has been adopted in some cases [9], [10], [17], [18], [19], a thorough and complete analysis based on a precise taxonomy of SAs has never been assessed in a rigorous way in previous works. In this paper we analyze this opportunity in details, showing to what extent interleaving can be applied, and how the possibility to use interleaving depends on the type of array and on the pipeline depth.…”

Section: Introductionmentioning

confidence: 99%

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Interleaving in Systolic-Arrays: A Throughput Breakthrough

Causapruno

Vacca

Graziano

et al. 2015

IEEE Trans. Comput.

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In past years the most common way to improve computers performance was to increase the clock frequency. In recent years this approach suffered the limits of technology scaling, therefore computers architectures are shifting toward the direction of parallel computing to further improve circuits performance. Not only GPU based architectures are spreading in consideration, but also Systolic Arrays are particularly suited for certain classes of algorithms. An important point in favor of Systolic Arrays is that, due to the regularity of their circuit layout, they are appealing when applied to many emerging and very promising technologies, like Quantum-dot Cellular Automata and nanoarrays based on Silicon NanoWire or on Carbon nanotube Field Effect Transistors. In this work we present a systematic method to improve Systolic Arrays performance exploiting Pipelining and Input Data Interleaving. We tackle the problem from a theoretical point of view first, and then we apply it to both CMOS technology and emerging technologies. On CMOS we demonstrate that it is possible to vastly improve the overall throughput of the circuit. By applying this technique to emerging technologies we show that it is possible to overcome some of their limitations greatly improving the throughput, making a considerable step forward toward the post-CMOS era.Index Terms-Systolic arrays, CMOS, QCA, molecular QCA, nanoMagnet logic, NanoWire field effect transistor, interleaving Ç The authors are with the

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Section: A Systematic Methods To Exploit Sa: Interleavingmentioning

confidence: 99%