Transforms and Quantization in the High-Throughput H.264/AVC Encoder Based on Advanced Mode Selection

Abstract

The H.264/AVC standard allows for a high compression efficiency at the cost of computational complexity. To achieve as high as possible efficiency, the proposed architecture supports the mode selection based on the rate-distortion optimization. In particular, the dataflow assumes throughput of 32 samples/coefficient per clock cycle, on average, allowing a lot of compression options to be checked. Moreover, the architecture supports all transform sizes specified for High Profile using the same hardware resources. Synthesis results show that the design can work at 100 MHz for FPGA Stratix II devices.

A Cost-Shared Quantization Algorithm and Its Implementation for Multi-Standard Video Codecs

“…The 8x8 transform and quantization for H.264 is presented in [20] and [21]. Several other designs based on H.264 codec have been reported in [22][23][24][25][26][27]. The authors in [28] present a design for the quantization for AVS.…”

“…The quantization unit computes the quantized value using multiplication and right shift operation. The architecture in [22] computes 4x4 and 8x8 transform, quantization, inverse transform and inverse quantization of H.264. The transform unit has eight parallel transform subunits each of which operates on one row/column.…”

“…The quantization unit also operates in parallel processing mode. The quantization module of [22] consists of 32 identical sub-quantizers. To support 32 quantizer sub-units this design needs 32 multipliers.…”

Variable Bit-Depth Processor for 8×8 Transform and Quantization Coding in H.264/AVC

“…An inverse quantizer based on 6-stage pipelined dual issue VLIW-SIMD architecture was proposed in (Lee, J.J. et al, 2008). (Pastuszak, 2008) presented an architecture in a FPGA capable of processing up to 32 coefficients per clock cycle. (Lee & Cho, 2008) proposed a scheme to be applied in several video compression standards such as JPEG, MPEG-1/2/4, H.264 and VC-1 where only one multiplier is used to minimize circuit size.…”

“…The architecture described in (Lee & Cho, 2008) and quantization for unified standard video CODEC (JPEG, MPEG-1/2/4, H.264 and VC-1). A high-throughput architecture which integrates forward transform, quantization, scaling, inverse transform and the sample reconstruction is presented in (Pastuszak, 2008). It uses reconfigurable 4×4 and 8×8 transform architecture and is able to process 32 samples/coefficients per clock cycle.…”