Transient Analysis of TSV Equivalent Circuit Considering Nonlinear MOS Capacitance Effects

Piersanti, Stefano; Paulis, Francesco de; Orlandi, Antonio; Swaminathan, Madhavan; Ricchiuti, V.

doi:10.1109/temc.2015.2414477

Cited by 37 publications

(4 citation statements)

References 23 publications

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“…However, there are some non-ideal factors in practical measurements. Examples of these non-idealities include the non-uniform thickness of RDLs, the nonuniform doping concentration of the silicon substrate, the roughness of the TSV surface, and the mismatch of the TSV radius and pitch [22]. In addition, the parasitic parameters of instruments, probes, and pads can also affect the measured inductance.…”

Section: S Smentioning

confidence: 99%

Modeling and Measurement of 3D Solenoid Inductor Based on Through-Silicon Vias

et al. 2023

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Through-silicon via (TSV) provides vertical interconnectivity among the stacked dies in three-dimensional integrated circuits (3D ICs) and is a promising option to minimize 3D solenoid inductors for on-chip radio-frequency applications. In this paper, a rigorous analytical inductance model of 3D solenoid inductor is proposed based on the concept of loop and partial inductance. And a series of 3D samples are fabricated on 12-in high-resistivity silicon wafer using low-cost standard CMOS-compatible process. The results of the proposed model match very well with those obtained by simulation and measurement. With this model, the inductance can be estimated accurately and efficiently over a wide range of inductor windings, TSV height, space, and pitch.

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Section: S Smentioning

confidence: 99%

Modeling and Measurement of 3D Solenoid Inductor Based on Through-Silicon Vias

et al. 2023

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“…As mentioned in the introduction, within the FDA method, which does not consider the mobile charge carriers, the RHS in (1) representing charge density at radius r can be rewritten as approximated qN a /ɛ Si , regardless of the minority carrier generation rate due to frequency. The analytical solution of the FDA expressed as the linear Poisson equation is suggested in [11][12][13][14][15][16]. However, to exactly analyse the temperature-and frequency-dependent characteristics of TSV MOS capacitance, we cannot neglect the mobile charge carriers in the silicon substrate.…”

Section: Analytical Modellingmentioning

confidence: 99%

“…However, as total power consumption increases with the increase of the frequency of switching operation, thermal factors affect the parasitic components of interconnections including TSVs and ICs. In particular, temperature-dependent metal-oxide semiconductor (MOS) effects in TSVs have an impact not only on signal delay and signal distortion from the RCdv/dt effect [9,10] but also on near-and far-end crosstalk by inducing a voltage [11,12], and these have been considered in previous research [10][11][12][13][14][15][16][17]. In order to analyse the MOS capacitance, most published research has used a numerical method using the Runge-Kutta method [10], analytical full depletion approximation (FDA) [11][12][13][14][15][16] or a semi-analytical method using maximum depletion width [17].…”

Section: Introductionmentioning

confidence: 99%

“…In particular, temperature‐dependent metal–oxide semiconductor (MOS) effects in TSVs have an impact not only on signal delay and signal distortion from the RC d v /d t effect [9, 10] but also on near‐ and far‐end crosstalk by inducing a voltage [11, 12], and these have been considered in previous research [10–17]. In order to analyse the MOS capacitance, most published research has used a numerical method using the Runge–Kutta method [10], analytical full depletion approximation (FDA) [11–16] or a semi‐analytical method using maximum depletion width [17]. Recently, a surface‐field‐based MOS capacitance model has been proposed to improve the FDA [18].…”

Section: Introductionmentioning

confidence: 99%

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Rigorous mathematical model of through‐silicon via capacitance

Kim

Hong-kyun

et al. 2018

IET Circuits, Devices & Systems

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Through-silicon vias (TSVs) are a key technology for three-dimensional integrated circuits. As the integration of circuits increases, high temperature has a greater effect on the performance of the TSV interconnections. The metal-oxide semiconductor (MOS) effect is one of the most important temperature-dependent characteristics of a TSV. This study introduces the mathematical model of a TSV to predict the MOS effect more accurately. The thermal effect that varies due to the change in the TSV capacitance and depletion region can be modelled by the non-linear the Poisson equation including mobile charge carriers. In procedures to solve this equation, the proposed method considers not only the thermal effect of intrinsic carrier concentration and silicon bandgap energy but also the shift effect of the flat band voltage due to the Si-SiO 2 interface charges. In addition, since it considers the minority carrier generation rate, which is dependent on the change of gate voltage, the MOS effect in a TSV can be explained more accurately using equations derived from these procedures. To verify the proposed mathematical model, comparison with the numerical method is carried out, and these results show that the proposed method is very accurate in explaining the MOS effect in a TSV.

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