Transient conduction in multidielectric silicon–oxide–nitride–oxide semiconductor structures

Abstract

The voltage- and time-dependence of the tunneling currents in polysilicon–oxide–nitride–oxide semiconductor structures have been investigated. Electron and hole contributions were separated using a shallow junction technique. The standard tunneling model for charge injection was successfully applied to describe the observed threshold voltage shifts. For both positive and negative gate voltages, the time-dependence of the current density through the tunneling oxide is given by a simple analytical equation. This equation is characterized by an initial time constant and an asymptotic t−1-dependence. At large programming times the current density follows the t−1-dependence, independent of the tunneling oxide thickness and applied voltage. Under positive polarity (write) electrons are injected from the substrate. Under negative polarity (erase) and previous injection electron back-tunneling rather than hole injection is dominant at the beginning of erasing. At the end of erasing, steady-state conduction can be dominated either by electrons or holes, depending on the applied voltage.

Impact of SiN Composition Variation on SANOS Memory Performance and Reliability Under nand (FN/FN) Operation

“…In contrast, the E transients of Si + nitrides (N3, N4) are relatively faster and saturate at lower E V FB values. Further improvement of E saturation can be achieved using a p+ polysilicon gate to suppress gate electron injection [32]. Similar SiN composition dependence of P/E transients was reported on SONOS devices with HTO as the BD [29], [30].…”

“…3. The two-slope ISPE characteristics demonstrate different physical regimes of charge conduction 2 -electron back tunneling to substrate at low E V G (only the state with excess electrons show E) and hole trapping in SiN at higher E V G [32]. For N + SiN erased from V FB = 5.5 V, the second phase of hole tunneling sets in at very high electric fields, followed by device breakdown as V FB becomes negative.…”

“…These devices have 12-nm-thick BD and 6-nm N2-type (see Table I) SiN trap layer. At the start of the P/E operation, the initial fields were computed using [32] …”

Impact of a HTO/Al2O3 bi-layer blocking oxide in nitride-trap non-volatile memories

“…The electron charges (Qn) injected in the conduction bands of the nitride layer are linked to the filling electron currents (Jinn/Joutn, respectively) from the substrate and control gate. Currents expressions include different tunnelling mechanisms (direct tunnelling, Fowler Nordheim (FN), or modified FN [11][12]), depending on the device configuration. The band bending induced by the charges trapped in the nitride layer is taken into account.…”

Capturing properties of a threefold coordinated silicon atom in silicon nitride: Positive correlation energy model

“…Its practical application is the use of amorphous Si 3 N 4 as a gate dielectric in the SONOS (silicon-oxide-nitrideoxide-semiconductor) field effect transistors. Although this memory effect has been discovered for more than thirty years and is widely used in modern silicon devices [2,[4][5][6][7][8], the exact nature and the kind of defects responsible for the carrier localization in the nitride film is still controversial. However, we already had a consensus that the localization of electrons and holes in the Si 3 N 4 film is related to the intrinsic defects created by the excess silicon atoms [2,4,8,9].…”