Transient Error Detection and Recovery in Processor Pipelines

Shazli, Syed Z.; Tahoori, Mehdi B.

doi:10.1109/dft.2009.38

Cited by 7 publications

(7 citation statements)

References 11 publications

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“…4 (e.g. [6]'s Checksum-based scheme). This simple strategy is not so efficient to sample the CED's results [15] [21], and then its recovery efficiency is moderate.…”

Section: Recovery Schemes For Dealing With Short and Long-duratimentioning

confidence: 99%

“…The current trend in solutions to cope with transient-fault effects is applying protection techniques at different abstraction levels of the design [3][4][5] [6]. The idea is thus to prevent the use of costly fault-tolerance mechanisms like the tripe modular redundancy, taking advantage of cheaper mitigation techniques that ensure satisfactory soft-error coverage for the system's most recurrent operations.…”

Section: Introductionmentioning

confidence: 99%

“…In case of misbehavior, an error flag is generated and the scheme can activate recovery mechanisms already implemented in modern systems for dealing with branch misprediction [4] [6]. After the transient fault disappearing, earlier faulty operation is thus repeated and the system returns to perform its normal computational sequence.…”

Section: Introductionmentioning

confidence: 99%

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A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic

et al. 2013

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-This paper presents a new recovery scheme for dealing with short-to-long duration transient faults in combinational logic. The new scheme takes earlier into account results of concurrent error detection (CED) mechanisms, and then it is able to perform shorter recovery latencies than existing similar strategy. The proposed scheme also requires less memory resources to save input contexts of combinational logic blocks. In addition, this work also proposes a taxonomy of CED techniques. It allows pointing out which are the necessary recovery resources as well as identifying which are the types of CED mechanisms that can be used with the new recovery scheme of this paper. The effectiveness of the proposed scheme was evaluated through electrical-level simulations. For all short-to-long duration transient-fault injections, it was never slower than state-of-art similar strategy, and indeed its recovery latency was faster for 34% of the simulated faulty scenarios.

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“…4 (e.g. [6]'s Checksum-based scheme). This simple strategy is not so efficient to sample the CED's results [15] [21], and then its recovery efficiency is moderate.…”

Section: Recovery Schemes For Dealing With Short and Long-duratimentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic

et al. 2013

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“…The today's trend in efficient protections against transient faults is applying mitigation techniques at different abstraction levels of the design [3,4]. The idea behind is the avoidance of costly faulttolerance mechanisms like triple modular redundancy, taking advantage of cheaper mitigation techniques that ensure satisfactory soft error coverage for the system's most recurrent operations.…”

Section: Introductionmentioning

confidence: 99%

Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode

Bastos

Torres

Natale

et al. 2012

Microelectronics Reliability

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a b s t r a c tThis work presents a novel circuit for detecting transient faults in combinational and sequential logic. The detection mechanism features a built-in current sensor connected to the bulks of the monitored logic. The proposed circuit was optimized in terms of power consumption and enhanced with low-power sleepmode. In addition, a calibration method for bulk built-in current sensors is presented. Overhead results indicate an increase of only 15% in power consumption which represents an improvement of factor 7 compared to similar existing sensors.Crown

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“…Concurrent error detection (CED) mechanisms are designed at lower abstraction levels while recovery-based error correction procedures (ECPs) at higher levels. This strategy takes advantage of recovery circuits that are already present in modern microprocessors to recompute instructions in case of branch misprediction [5] [6]. Then, only CED mechanisms need to be implemented, and as they are optimized at lower levels, they can monitor circuit's fault-prone nodes much closer than higher-level schemes could.…”

Section: Introductionmentioning

confidence: 99%

A New Bulk Built-In Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron Technologies

Bastos

Natale

Flottes

et al. 2011

2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

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Abstract-Today's deeply-scaled technology-based integrated circuits are highly sensitive to soft error, tending to be even more in the future. In fact, emerging critical issues are related to transient faults that now can be as long as circuits' clock periods. This work presents a novel improved strategy based on bulk built-in current sensors that is able to cope with long-duration transient faults. Our cost-effective approach is a concurrent error detection scheme with recovery procedure, and rather than existing similar strategy, it has faster correction latency and uses less recovery resources.

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Transient Error Detection and Recovery in Processor Pipelines

Cited by 7 publications

References 11 publications

A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic

A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic

Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode

A New Bulk Built-In Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron Technologies

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