Transient non-linear thermal FEM simulation of smart power switches and verification by measurements

Kosel, V.; Sleik, Roland; Glavanovics, Michael

doi:10.1109/therminic.2007.4451757

Cited by 14 publications

(6 citation statements)

References 8 publications

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“…Due to the electric power dissipation, the DUTs heat up (to T peak ) and cool down (to T case ) during each stress pulse. The induced temperature rise (

Δ T

) can either be simulated with the finite‐element method (FEM) or it can be approximated analytically from P max measurements of energy ramp‐up (ERU) tests by:

Δ T = T_{dest} - T_{case} = k_{th} \cdot (P_{\max} \cdot {(t_{p})}^{N} .

In Equation T dest denotes the device‐specific destruction temperature. This is the temperature where the device fails at the first stress pulse (i.e., the safe operating area (SOA) limit).…”

Section: Data and Challengesmentioning

confidence: 99%

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Bayesian Network Model with Application to Smart Power Semiconductor Lifetime Data

2015

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In this article, Bayesian networks are used to model semiconductor lifetime data obtained from a cyclic stress test system. The data of interest are a mixture of log-normal distributions, representing two dominant physical failure mechanisms. Moreover, the data can be censored due to limited test resources. For a better understanding of the complex lifetime behavior, interactions between test settings, geometric designs, material properties, and physical parameters of the semiconductor device are modeled by a Bayesian network. Statistical toolboxes in MATLAB® have been extended and applied to find the best structure of the Bayesian network and to perform parameter learning. Due to censored observations Markov chain Monte Carlo (MCMC) simulations are employed to determine the posterior distributions. For model selection the automatic relevance determination (ARD) algorithm and goodness-of-fit criteria such as marginal likelihoods, Bayes factors, posterior predictive density distributions, and sum of squared errors of prediction (SSEP) are applied and evaluated. The results indicate that the application of Bayesian networks to semiconductor reliability provides useful information about the interactions between the significant covariates and serves as a reliable alternative to currently applied methods.

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“…Due to the electric power dissipation, the DUTs heat up (to T peak ) and cool down (to T case ) during each stress pulse. The induced temperature rise (

Δ T

) can either be simulated with the finite‐element method (FEM) or it can be approximated analytically from P max measurements of energy ramp‐up (ERU) tests by:

Δ T = T_{dest} - T_{case} = k_{th} \cdot (P_{\max} \cdot {(t_{p})}^{N} .

In Equation T dest denotes the device‐specific destruction temperature. This is the temperature where the device fails at the first stress pulse (i.e., the safe operating area (SOA) limit).…”

Section: Data and Challengesmentioning

confidence: 99%

“…Due to the electric power dissipation, the DUTs heat up (to T peak ) and cool down (to T case ) during each stress pulse. The induced temperature rise ( T) can either be simulated with the finite-element method (FEM) (8,9) or it can be approximated analytically from P max measurements of energy ramp-up (ERU) tests by: (1,10)…”

Section: Electro-thermal Effectsmentioning

confidence: 99%

Bayesian Network Model with Application to Smart Power Semiconductor Lifetime Data

2015

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“…Testing is in most cases to be done at the minimum specified operating temperature, which generally means -40°C for automotive devices, causing the maximum thermal stress to occur when the device shuts down at a protection level of typically 170°C, [8]. …”

Section: Representative Measurements Of Industry Standard High Currenmentioning

confidence: 99%

A compact high current system for short circuit testing of smart power switches according to AEC standard Q100-012

Glavanovics¹,

Sleik²,

Schreiber

2008

2008 IEEE Power Electronics Specialists Conference

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The short circuit robustness of smart power switches has become a major concern in automotive applications over the last years. This is reflected in a new extension to the AEC qualification standard Q100-12, where the basic requirements for short circuit testing of "smart" switches with integrated overcurrent protection are given. This paper describes the practical implementation of a compact test setup for the laboratory measurement of short circuit events with initial peak currents as high as 1000A at supply voltages up to 60V. The AEC standard further requires a low-ohmic test circuit with well-defined impedances. This is usually achieved by arrangement of a large DC power supply with discrete copper bus bars, massive test fixtures and solenoid type air coils to achieve well-defined resistance and inductance values. Our novel approach utilizes a compact printed circuit board arrangement instead, replacing large copper cross sections by short distances and optimized geometries to achieve the same performance at a fraction of the cost and space requirements.To protect the equipment from potential hazard of fire in case of a destructive device failure without sacrificing performance, fast overcurrent detection is required as well as shutdown and removal of energy from the tested device within microseconds. This can be achieved with low-cost offthe-shelf current sensors and surface-mounted MOSFET switches by careful consideration of their specified properties.Representative measurements of industry standard high current smart power switches show that the presented test equipment meets the requirements of Q100-12 for laboratory short circuit measurements.

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“…Thermal material properties are taken from manufacturers' datasheets for every modeled part respectively. Thermal material properties of the silicon chip are modeled as temperature dependent according to the material models presented in [4], which we have validated for simulations of Smart Power Switches in [5]. …”

Section: B Sps Device and Its Fem Modelmentioning

confidence: 99%

Evaluation of an electrical method for detection of die attach imperfections in Smart Power Switches using transient thermal FEM simulations

Kosel

Glavanovics

Scheikl

2008

2008 14th International Workshop on Thermal Inveatigation of ICs and Systems

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A method for detection of die attach imperfections in Smart Power Switches is evaluated using non-linear transient thermal FEM simulations and measurements. This method employs smart functions of SPS devices such as overcurrent and over-temperature protection. The protective thermal shut down function is triggered by the temperature of the integrated temperature sensor. The temperature rise depends on power dissipation in the device and on the thermal junction to ambient impedance which is inter alia related to the die attach imperfection. The evaluation is performed on a two channel Smart Power Switch. Results are focused on practical relevance and sensitivity of this method to the influence of die attach thickness and die attach voids.

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Transient non-linear thermal FEM simulation of smart power switches and verification by measurements

Cited by 14 publications

References 8 publications

Bayesian Network Model with Application to Smart Power Semiconductor Lifetime Data

Bayesian Network Model with Application to Smart Power Semiconductor Lifetime Data

A compact high current system for short circuit testing of smart power switches according to AEC standard Q100-012

Evaluation of an electrical method for detection of die attach imperfections in Smart Power Switches using transient thermal FEM simulations

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