Split-drain magnetic field-effect transistor (SD-MAGFET) has been widely used as magnetic field sensors, current sensors and temperature-stable arrays due to its small size and CMOS compatibility [1]-[2][3]. Previous work suggested that its sensitivity hysteresis could be caused by the Si/SiO2 interface traps at the sidewalls of the conduction channel [4]. However, the effects of these interface traps on the magnetic sensitivity have not been studied in detail. In this work, the effects of trap type, trap density and trap energy are investigated by Silvaco TCAD.