Transistency Models: Memory Ordering at the Hardware-OS Interface

Lustig, Daniel; Sethi, Geet; Bhattacharjee, Abhishek; Martonosi, Margaret

doi:10.1109/mm.2017.69

Cited by 17 publications

(63 citation statements)

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“…VM is a complicated interface requiring correct hardware and software cooperation. Despite decades of active research, real-world VM implementations routinely suffer from bugs in both the hardware and OS layers [5,80,94]. The advent of hardware accelerators and new memory technologies promises new hardware and software VM management layers, which add to this already challenging verification burden.…”

Section: Issues With Modern Virtual Memorymentioning

confidence: 99%

“…Therefore, on every load and store operation, the accessed page's page table entry must have its accessed bit set. On modern CPUs, the page table walker is responsible for setting the accessed bit [19,80,94]. In other words, when there is a TLB miss and a page table walk is performed, the page table walker hardware identifies the desired page table entry and sets the accessed bit in it.…”

Section: Accessed and Dirty Bitsmentioning

confidence: 99%

“…2. Dirty bits are used to identify memory-resident pages with data that needs to be written back to the stale backing-store [80,94]. Much like dirty cache lines, this bit is set when a store instruction writes to a page.…”

Section: Accessed and Dirty Bitsmentioning

confidence: 99%

“…Likewise, Bornholt et al introduced the notion of a consistency model for filesystems, which live on disk as opposed to memory [24]. Lustig et al introduced the term transistency model for memory models that take page table entry status bits into account in ways that consistency models alone cannot describe [80]. The latter two introduce the Ferrite and COATCheck tools, respectively, each of which applies formal memory model analysis techniques to their respective domains.…”

Section: Memory Models and The Virtual Memory Subsystemmentioning

confidence: 99%

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Architectural and Operating System Support for Virtual Memory

Bhattacharjee

Lustig

Martonosi

2017

Synthesis Lectures on Computer Architecture

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This book provides computer engineers, academic researchers, new graduate students, and seasoned practitioners an end-to-end overview of virtual memory. We begin with a recap of foundational concepts and discuss not only state-of-the-art virtual memory hardware and software support available today, but also emerging research trends in this space. The span of topics covers processor microarchitecture, memory systems, operating system design, and memory allocation. We show how efficient virtual memory implementations hinge on careful hardware and software cooperation, and we discuss new research directions aimed at addressing emerging problems in this space. Virtual memory is a classic computer science abstraction and one of the pillars of the computing revolution. It has long enabled hardware flexibility, software portability, and overall better security, to name just a few of its powerful benefits. Nearly all user-level programs today take for granted that they will have been freed from the burden of physical memory management by the hardware, the operating system, device drivers, and system libraries. However, despite its ubiquity in systems ranging from warehouse-scale datacenters to embedded Internet of Things (IoT) devices, the overheads of virtual memory are becoming a critical performance bottleneck today. Virtual memory architectures designed for individual CPUs or even individual cores are in many cases struggling to scale up and scale out to today's systems which now increasingly include exotic hardware accelerators (such as GPUs, FPGAs, or DSPs) and emerging memory technologies (such as non-volatile memory), and which run increasingly intensive workloads (such as virtualized and/or "big data" applications). As such, many of the fundamental abstractions and implementation approaches for virtual memory are being augmented, extended, or entirely rebuilt in order to ensure that virtual memory remains viable and performant in the years to come.

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Section: Issues With Modern Virtual Memorymentioning

confidence: 99%

Section: Accessed and Dirty Bitsmentioning

confidence: 99%

Section: Accessed and Dirty Bitsmentioning

confidence: 99%

Section: Memory Models and The Virtual Memory Subsystemmentioning

confidence: 99%

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Architectural and Operating System Support for Virtual Memory

Bhattacharjee

Lustig

Martonosi

2017

Synthesis Lectures on Computer Architecture

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“…To augment MCMs with VM-aware features, prior work proposed memory transistency models (MTMs): "the superset of [memory] consistency [models] which capture all [address] translation-aware sets of ordering rules" [29]. Likewise, where ISA MCM behaviors are typically specified and validated using small diagnostic programs called litmus tests (such as sb in Fig.…”

Section: Introductionmentioning

confidence: 99%

TransForm: Formally Specifying Transistency Models and Synthesizing Enhanced Litmus Tests

Hossain

Trippel

Martonosi

2020

2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)

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Memory consistency models (MCMs) specify the legal ordering and visibility of shared memory accesses in a parallel program. Traditionally, instruction set architecture (ISA) MCMs assume that relevant program-visible memory ordering behaviors only result from shared memory interactions that take place between user-level program instructions. This assumption fails to account for virtual memory (VM) implementations that may result in additional shared memory interactions between user-level program instructions and both 1) system-level operations (e.g., address remappings and translation lookaside buffer invalidations initiated by system calls) and 2) hardware-level operations (e.g., hardware page table walks and dirty bit updates) during a user-level program's execution. These additional shared memory interactions can impact the observable memory ordering behaviors of user-level programs. Thus, memory transistency models (MTMs) have been coined as a superset of MCMs to additionally articulate VM-aware consistency rules. However, no prior work has enabled formal MTM specifications, nor methods to support their automated analysis. To fill the above gap, this paper presents the TransForm framework. First, TransForm features an axiomatic vocabulary for formally specifying MTMs. Second, TransForm includes a synthesis engine to support the automated generation of litmus tests enhanced with MTM features (i.e., enhanced litmus tests, or ELTs) when supplied with a TransForm MTM specification. As a case study, we formally define an estimated MTM for Intel x86 processors, called x86t elt, that is based on observations made by an ELT-based evaluation of an Intel x86 MTM implementation from prior work and available public documentation [23, 29]. Given x86t elt and a synthesis bound (on program size) as input, TransForm's synthesis engine successfully produces a complete set of ELTs (for synthesis bounds that complete within one week) including relevant hand-curated ELTs from prior work, plus over 100 more.

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UCLID5: Multi-modal Formal Modeling, Verification, and Synthesis

Polgreen

Cheang

Gaddamadugu

et al. 2022

Computer Aided Verification

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UCLID5 is a tool for the multi-modal formal modeling, verification, and synthesis of systems. It enables one to tackle verification problems for heterogeneous systems such as combinations of hardware and software, or those that have multiple, varied specifications, or systems that require hybrid modes of modeling. A novel aspect of UCLID5 is an emphasis on the use of syntax-guided and inductive synthesis to automate steps in modeling and verification. This tool paper presents new developments in the UCLID5 tool including new language features, integration with new techniques for syntax-guided synthesis and satisfiability solving, support for hyperproperties and combinations of axiomatic and operational modeling, demonstrations on new problem classes, and a robust implementation.

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Transistency Models: Memory Ordering at the Hardware-OS Interface

Cited by 17 publications

References 10 publications

Architectural and Operating System Support for Virtual Memory

Architectural and Operating System Support for Virtual Memory

TransForm: Formally Specifying Transistency Models and Synthesizing Enhanced Litmus Tests

UCLID5: Multi-modal Formal Modeling, Verification, and Synthesis

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