Transistor-Level Synthesis for Low-Power Applications

Abstract

An important factor which greatly affects the power consumption and the delay of a circuit is the input capacitance of its gates. High input capacitances increase the power consumption as well as the time for charging and discharging the inputs. Current approaches address this problem either through gate-level only resynthesis and optimization, or indirectly through transistor-level synthesis aimed for transistor count reduction. In this paper a method is presented to synthesize complex gates at the transistor level with explicit consideration of the switching activity profile for the gate. The method finds a power efficient implementation by giving priority to transistor inputs with higher switching activity, while keeping the overall number of required transistors low. Experimental results demonstrate the benefit of the approach.

Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering

“…As the detailed derivation was already presented by other authors, the reader is pointed to references [22,23] for further details. The methods for transistor network generation presented in [7,8,9] are potentially better than the ones derived from BDDs [22,23]. This is a consequence of the fact that BDDs assume bidirectional switches, which is not a restriction to the approach in [7,8,9].…”

“…The methods for transistor network generation presented in [7,8,9] are potentially better than the ones derived from BDDs [22,23]. This is a consequence of the fact that BDDs assume bidirectional switches, which is not a restriction to the approach in [7,8,9]. However, for functions with four or less inputs, the difference in the number of transistors is not significant as reported in [7].…”

“…Indeed, design migration from FPGAs to ASICs is done in a way to preserve the regularity [2,14]. Recently, different methods for generating cell level transistor networks have been proposed [3,7,8,9,16,18]. These methods can be used to retarget FPGAs to ASICs [2,14], as FPGAs are based on look-up tables (LUTs) implementing four input functions as a single block.…”

“…Some approaches to transistor reordering are restricted to series transistor swapping in series parallel networks [1]. This approach is therefore not applicable to functions derived from FPGA look-up tables, as they may contain networks that are best implemented with networks that are not series parallel [3,7,8,9,16]. Other approaches create a functional description (normally a BDD -Binary decision diagram), which is ordered and then decomposed [6,19].…”

Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell

“…Computer-Aided Design (CAD) tools for standard cell layout design are proposed to reduce the design cost of standard cell libraries. Device level synthesis has been proposed to generate optimal layout from schematic, considering optimal both geometrical placing and sizing of transistors and signal wires [1], [2]. Device level synthesis has a potential to generate optimal circuit layout, however, this technique has too much flexibility thus it is difficult for implementation.…”