Transistor sizing for low power CMOS circuits

Borah, M.; Owens, R.M.; Irwin, M.J.

doi:10.1109/43.503935

Cited by 62 publications

(22 citation statements)

References 16 publications

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“…In order to quantify the amount of power saved, we use previously-reported research to estimate the amount of power that various functional units use [16,17,18]. From these sources we obtain power estimates assuming dynamic logic and relatively fast carry lookahead adders.…”

Section: Power Resultsmentioning

confidence: 99%

Dynamically exploiting narrow width operands to improve processor power and performance

Brooks

Martonosi

1999

Proceedings Fifth International Symposium on High-Performance Computer Architecture

226

177

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Section: Power Resultsmentioning

confidence: 99%

Dynamically exploiting narrow width operands to improve processor power and performance

Brooks

Martonosi

1999

Proceedings Fifth International Symposium on High-Performance Computer Architecture

226

177

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show abstract

“…In order to quantify the amount of power saved, we use previously reported research to estimate the amount of power that various functional units use [Borah et al 1996;Ng et al 1996;Zimmermann and Fichtner 1997;Callaway and Swartzlander 1997]. From these sources we obtain power estimates assuming dynamic logic and relatively fast carry look-ahead adders.…”

Section: Power Results: Overviewmentioning

confidence: 99%

Value-based clock gating and operation packing

Brooks

Martonosi

2000

ACM Trans. Comput. Syst.

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The large address space needs of many current applications have pushed processor designs toward 64-bit word widths. Although full 64-bit addresses and operations are indeed sometimes needed, arithmetic operations on much smaller quantities are still more common. In fact, another instruction set trend has been the introduction of instructions geared toward subword operations on 16-bit quantities. For example, most major processors now include instruction set support for multimedia operations allowing parallel execution of several subword operations in the same ALU. This article presents our observations demonstrating that operations on "narrow-width" quantities are common not only in multimedia codes, but also in more general workloads. In fact, across the SPECint95 benchmarks, over half the integer operation executions require 16 bits or less. Based on this data, we propose two hardware mechanisms that dynamically recognize and capitalize on these narrow-width operations. The first, power-oriented optimization reduces processor power consumption by using operand-value-based clock gating to turn off portions of arithmetic units that will be unused by narrow-width operations. This optimization results in a 45%-60% reduction in the integer unit's power consumption for the SPECint95 and MediaBench benchmark suites. Applying this optimization to SPECfp95 benchmarks results in slightly smaller power reductions, but still seems warranted. These reductions in integer unit power consumption equate to a 5%-10% full-chip power savings. Our second, performance-oriented optimization improves processor performance by packing together narrow-width operations so that they share a single arithmetic unit. Conceptually similar to a dynamic form of MMX, this optimization offers speedups of 4.3%-6.2% for SPECint95 and 8.0%-10.4% for MediaBench. Overall, these optimizations highlight an increasing opportunity for value-based optimizations to improve both power and performance in current microprocessors.

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“…They developed several algorithms to minimize resources as power, speed and silicon area in one objective while restricting the other resources by an upper bound. Borah et al [4] minimize power while constraining the delay time.…”

Section: Background and Related Workmentioning

confidence: 99%

Integrated circuit optimization by means of evolutionary multi-objective optimization

Blesken

Chebil

Rueckert³

et al. 2011

Proceedings of the 13th Annual Conference on Genetic and Evolutionary Computation

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The design of resource efficient integrated circuits (ICs) requires solving a minimization problem which consists of more than one objective given as measures of the available resources. This multi-objective optimization problem (MOP) can be solved on the smallest unit of the IC, the standard cells, to improve the performance of the entire circuit. In this work, transistor sizing of an IC is approached via a multi-objective approach which includes the use of multiobjective evolutionary algorithms (MOEAs). We compare the performance of two MOEAs on a four-dimensional MOP of a particular standard cell. The results indicate that evolutionary strategies are suitable for the treatment of such problems and advantageous against other rather classical methods.

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Transistor sizing for low power CMOS circuits

Cited by 62 publications

References 16 publications

Dynamically exploiting narrow width operands to improve processor power and performance

Dynamically exploiting narrow width operands to improve processor power and performance

Value-based clock gating and operation packing

Integrated circuit optimization by means of evolutionary multi-objective optimization

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