Transistor sizing issues and tool for multi-threshold CMOS technology

Abstract

Multi-threshold CMOS is an increasingly popular circuit approach that enables high performance and low power operation. However, no methodologies have been developed to size the high V t sleep transistor in an intelligent manner that trades off area and performance. In fact, many attempts at sizing the sleep transistor without close consideration of input vector patterns or internal structures can lead to large overestimates or large underestimates in sleep transistor sizing. This paper describes some of the issues involved in sizing transistors for MTCMOS and also introduces a variable breakpoint switch level simulator that can rapidly calculate delay in MTCMOS circuits as functions of design variables such as V dd , V t , and sleep transistor sizing. BACKGROUNDPower consumption in conventional CMOS circuits can be attributed to switching power, leakage power, and short circuit power. Switching power is usually the dominant term and is given by the well known formula:where α is the activity factor, C L is the total load capacitance, V dd is the supply voltage, and f clk is the clock frequency.Clearly, to reduce this energy dissipated to charge and discharge load capacitances, the circuit designer's optimum choice is to scale the supply voltage down. However, in order to maintain performance, the threshold voltage should also be scaled down as well so that the gate drive, (V gs -V t ), remains large enough, since propagation delay in a CMOS gate can be approximated as:where α is for modeling short channel effects [1] [2]. By reducing V dd , the switching power is reduced quadratically, but a reduction in V t causes an exponential increase in subthreshold leakage current. As one continues to scale down V dd and V t , the increased leakage power can dominate the dynamic switching power [3].In many event driven applications, like a processor running an X-server, circuits spend most of their time in an idle state where noPermission to make digital/hard copy of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage, the copyright notice, the title of the publication and its date appear, and notice is given that copying is by permission of ACM, Inc. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and /or a fee." DAC 97, Anaheim, California (c) 1997 ACM 0-89791-920-3/97/06 ..$3.50 computation is being performed, so large subthreshold leakage becomes unacceptable. Multi-threshold CMOS was developed in order to reduce this leakage current during idle modes by providing a high threshold "gating" transistor in series with the low V t circuit transistors. In active mode, the high V t transistor is turned on, while in sleep mode it is turned off, providing a small subthreshold leakage current [4]. For a purely combinational circuit, where state does not need to be preserved, only one type of high V t device is actually required. The NMOS is preferable be...

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