Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits

Abstract

Abstract-This paper presents transistor variability modeling and its validation for body-biased subthreshold circuits based on measurements of a device-array circuit using a 90-nm technology. The device array consists of p/nMOS transistors and ring oscillators. We examine and confirm the correlation between the performance variation model extracted from measured I-V characteristics and fabricated oscillation frequencies. We demonstrate that delay variations in subthreshold circuits are well characterized with two parameters, i.e., threshold voltage and subthreshold swing parameter. We also reveal that threshold voltage shift by body biasing can be deterministically modeled and statistical modeling is less meaningful.

Within-die and die-to-die variability on 65nm CMOS : oscillators experimental results

“…Simply an odd number of inverters connected sequentially in a feedback loop, for a given temperature and a number of inverter stages, the oscillation frequency depends only fan-outs and on physical aspects of the CMOS fabrication process. The use of ROs for monitoring process variations has been a long-standing practice [5], [6], [7], [8]. The RO oscillating frequency shifts, as a result of both within-die (WID) and Die-to-die (D2D) variations, need an analysis to separate the influence of each (WID vs. D2D), and also to characterize this shift as a result of a given set of process parameters.…”

(Invited) Robust Subthreshold Circuit Design to Manufacturing and Environmental Variability

“…The rise in temperature decreases V th , which causes speeding up the circuit, whereas the rise in temperature decreases μ, which results in the degradation of the circuit delay. This means that the influence of temperature on the circuit delay depends on the supply voltage (29). Figure 6 illustrates the simulated oscillation frequency in a 17-stage RO as a function of temperature.…”

“…We are working for putting subthreshold circuits robust to practical use at device, circuit and CAD levels. At device level, we constructed a transistor variability model that reproduces subthreshold circuit performance (29), and evaluated soft error immunity of subthreshold SRAM (30)(31)(32). At circuit level, adaptive performance control is studied parting from conventional worst-case design (33).…”