Transition-Code Based Linearity Test Method for Pipelined ADCs With Digital Error Correction

Lin, Jhih-Min; Chang, Soon-Jyh; Kung, Te-Chieh; Ting, Hsin-Wen; Huang, Chih‐Hao

doi:10.1109/tvlsi.2010.2089543

Cited by 22 publications

(24 citation statements)

References 22 publications

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“…5, the third and sixth errors (TE 1 ) occur because of faults in stage 1, whereas the others (TE 2 ) occur because of faults in stage 2. Theoretically, the gain faults of stage 1 cause transition errors at the 3/8 and 5/8 points [8]. On the same principle, the gain faults at the j th stage generate transition points at 3=2 jþ2 ; 5=2 jþ2 ; .…”

Section: Applying the Stage Faultsmentioning

confidence: 96%

“…Simultaneously, the residues are determined through the sub-DAC, subtractor, and gain stage, and they are delivered to the next stage. The outputs at each stage are stored in the pipeline latches and passed through the digital error correction (DEC) circuits, after which the final outputs are determined by eliminating errors including a large amount of comparator offsets [8].…”

Section: Faults In Pipelined Adcmentioning

confidence: 99%

“…In this letter, we target the gain fault and op-amp offset fault in MDAC which directly affect the linearity of pipelined ADCs. The fault effects caused by comparator offsets are not considered, because pipelined ADCs with DEC circuits can tolerate large comparator offset faults, especially in the 1.5-bit/stage pipelined structure [8,10].…”

Section: Faults In Pipelined Adcmentioning

confidence: 99%

“…The length of each section where the values are "00," "01," and "10" representing the results of sub-histogram are calculated mathematically as shown in (7). A simple method to find gain j is to use l 01 , the results of which are shown in (8). …”

Section: Calculation Of Pipeline Stage Faultsmentioning

confidence: 99%

“…To solve these problems, many reduced-code test methods have been proposed. In [8], a transition-code-based method that measures a few specific transition codes was proposed to reduce test data. Transition codes, which refer to specific codes that include a large nonlinearity in the presence of a gain fault, are measured for the reduction of test samples.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Reduced-code test method using sub-histograms for pipelined ADCs

Son

Jang

Kim

et al. 2015

IEICE Electron. Express

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The measurement of static test parameters for an analog-todigital converter (ADC) requires a large volume of test data, especially for a high-resolution ADC. This paper proposes a reduced-code test method for pipelined ADCs that does not compromise test accuracy. The proposed method calculates fault information at each stage by using sub-histograms. The simulation results based on 12-bit pipelined ADCs show a maximum integral nonlinearity error of 0.590 LSB with only 3.92% of the codes required for the conventional histogram-based method.

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Section: Applying the Stage Faultsmentioning

confidence: 96%

Section: Faults In Pipelined Adcmentioning

confidence: 99%

Section: Faults In Pipelined Adcmentioning

confidence: 99%

Section: Calculation Of Pipeline Stage Faultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Reduced-code test method using sub-histograms for pipelined ADCs

Son

Jang

Kim

et al. 2015

IEICE Electron. Express

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Simulink Behavioral Modeling of a 10- bit Pipelined ADC

Barra

Kouda

Dendouga

et al. 2013

Int. J. Autom. Comput.

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The increasing architecture complexity of data converters makes it necessary to use behavioral models to simulate their electrical performance and to determine their relevant data features. For this purpose, a specific data converter simulation environment has been developed which allows designers to perform time-domain behavioral simulations of pipelined analog to digital converters (ADCs). All the necessary blocks of this specific simulation environment have been implemented using the popular Matlab simulink environment. The purpose of this paper is to present the behavioral models of these blocks taking into account most of the pipelined ADC non-idealities, such as sampling jitter, noise, and operational amplifier parameters (white noise, finite DC gain, finite bandwidth, slew rate, and saturation voltages). Simulations, using a 10-bit pipelined ADC as a design example, show that in addition to the limits analysis and the electrical features extraction, designers can determine the specifications of the basic blocks in order to meet the given data converter requirements.

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Low-cost methodology for fault diagnosis and localization in pipelined ADCs

Abbas

Ramadan

2018

Integration

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Transition-Code Based Linearity Test Method for Pipelined ADCs With Digital Error Correction

Cited by 22 publications

References 22 publications

Reduced-code test method using sub-histograms for pipelined ADCs

Reduced-code test method using sub-histograms for pipelined ADCs

Simulink Behavioral Modeling of a 10- bit Pipelined ADC

Low-cost methodology for fault diagnosis and localization in pipelined ADCs

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