Translating Timed I/O Automata Specifications for Theorem Proving in PVS

Abstract

The timed input/output automaton modeling framework is a mathematical framework for specification and analysis of systems that involve discrete and continuous evolution. In order to employ an interactive theorem prover in deducing properties of a timed input/output automaton, its statetransition based description has to be translated to the language of the theorem prover. This thesis describes a tool for translating from TIOA, the formal language for describing timed input/output automata, to the language of the Prototype Verification System (PVS)--a specification system with an integrated interactive theorem prover. We describe the translation scheme, discuss the design decisions, and briefly present case studies to illustrate the application of the translator in the verification process.

Specifying and proving properties of timed I/O automata using Tempo

“…The translation scheme followed uses a PVS theory template which is instantiated with the states, actions and transitions of an automaton. A tool [19,22] developed as part of Tempo performs the translation automatically. The PVS theory template used in the translation scheme is a new variant of the TAME (Timed Automata Modeling Environment) [3,5] automaton template, whose original variants supported modeling and proving properties of MMT automata [29] and SCR automata [15].…”

“…1, which we reproduce from [22]. The methodology, updated since publication of [22], involves (1) writing the specification of a system and its properties in the TIOA language, (2) using the translator tool to generate the PVS equivalent of the system as an instantiation of the TAME4TIOA template, and then (3) proving the properties in PVS using TAME4TIOA strategies. The user describes the system in the TIOA language using the state-transition structure.…”

“…Our implementation of the TIOA-to-PVS translator described in [22] builds upon [7]. The target PVS specifications of this translator strongly resemble TAME specifications.…”

Convergence Verification: From Shared Memory to Partially Synchronous Systems

“…We have developed a PVS [19] theory for verifying partially synchronous pattern formation protocols within the exiting Timed I/O Automata/PVS framework [3,15]. The theory formalizes partially synchronous systems as described in this paper, and we have verified the convergence of the example presented here.…”

“…First, we specify the shared state version of the protocol in PVS and verify its convergence using the pre-existing PVS metatheory [17] . We obtain the partially synchronous version of the pattern formation system; this is specified in PVS using the PVS/TIOA toolset [15] and we show that it satisfies the assumptions required for convergence.…”