Transmitter and channel equalization for high-speed server interconnects

Araujo, D.N. de; Diepenbrock, J.C.; Cases, M.; Pham, N.

doi:10.1109/epep.2003.1250036

Cited by 15 publications

(6 citation statements)

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“…In parallel with such a drastic increase in the level of integration, high-speed digital systems have achieved data rates in excess of several tens of gigabits per second (Gb/s), which require several tens of gigahertz of interconnect bandwidth in both on-chip and off-chip [3], [4]. However, since interconnect lines cannot be scaled down as much as transistors, interconnect latency and bandwidth may dominate system performance [5]- [7]. In particular, signal integrity exacerbation due to interconnect lines may play a decisive role in the performance of high-speed digital systems [8], [9].…”

Section: Introductionmentioning

confidence: 99%

Analytical Eye-Diagram Determination for the Efficient and Accurate Signal Integrity Verification of Single Interconnect Lines

Kim

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In this paper, a new efficient and accurate analytical eye-diagram determination technique for interconnect lines is presented. The simplest input test signal model for the intersymbol interference analysis of high-speed data links is mathematically formulated. Since input test patterns for eye boundaries are determined analytically, it is considered very convenient and efficient. The proposed technique shows excellent agreement with the SPICE-based simulation in both eye height and jitter, i.e., within 5% error for nondiscontinuous data paths and 10% error for discontinuous data paths. The method is much more computation-time-efficient than the pseudorandom bit sequence-based SPICE simulation in the order of magnitude.Index Terms-Eye diagram, intersymbol interference (ISI), jitter, signal integrity, transmission line.

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Section: Introductionmentioning

confidence: 99%

Analytical Eye-Diagram Determination for the Efficient and Accurate Signal Integrity Verification of Single Interconnect Lines

Kim

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Two distinct PRBS input signals are generated with a 16-stage linear feedback shift register (LFSR) composed of [16,13,9,6] and [16,10,7,4] feedback taps.…”

Section: Verification Of the Proposed Techniquementioning

confidence: 99%

“…In high-speed digital systems, signal integrity exacerbation due to interconnect lines significantly limits circuit performance [1][2][3][4][5][6][7][8][9]. Thus, the signal integrity verification of interconnect lines has become an integral part of the system design.…”

Section: Introductionmentioning

confidence: 99%

Analytical Eye-Diagram Determination for the Efficient and Accurate Signal Integrity Verification of Coupled Interconnect Lines

Lee¹,

Kim²,

Eo³

2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-A new efficient analytical eye-diagram determination technique for coupled interconnect lines is presented. Two coupled lines are decoupled into isolated eigen modes; bit blocks for coupled lines, which are defined as a block of consecutive bits, are then represented with decoupled modes. The crosstalk effects within the bit blocks are taken into account. Thereby, the crucial input bit patterns for the worst case eye-diagram determination are modeled mathematically, including inter-symbol interference (ISI). The proposed technique shows excellent agreement with the SPICE-based simulation. Furthermore, it is very computation-time-efficient in the order of magnitude, compared with the SPICE simulation, which requires numerous pseudo-random bit sequence (PRBS) input signals.

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“…Cost of optical links have been decreasing, however, electrical links have been extended with the use of increased levels of transmitter feed-forward equalization, receiver side equalization such as adaptive and decision feedback equalization (DFE), improved channel design tools, lower loss materials as well as external methods such as discrete equalization and distributed cable equalization [18] to remain competitive.…”

Section: Future Directionsmentioning

confidence: 99%

Complex high speed links in server environments

Araujo

Matoglu

Cases

et al.

Proceedings Electronic Components and Technology, 2005. ECTC '05.

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Complex interconnects for server links pose a design challenge due to many components, interactions and tradeoffs. This paper examines the evolution, design choices, current challenges, and future directions of such high speed links in a scalable server setting. I. IntroductionAs performance requirements for high-end servers increase, designers are faced with systems\ demands for high speed links to provide data transport within and across computation nodes for increased bandwidth. As new technologies such as hyper-threading and multi-core processors become more prevalent, this places even higher demands on the signaling and interconnect. Despite high losses and interconnect type transitions, the speed and range of copper electrical links have been continuously extended due to innovative designs. A careful balance and tradeoff between cost and performance at every level is needed to stay competitive in the high performance, high volume server market.While most standards for high speed links have provisions for simpler topologies such as agent to agent on the same board, across boards through a connector, in a backplane environment with two connectors, or in a simple cabled configuration [1], more complex topologies are rarely covered due to the vast number of design tradeoffs and interoperability issues. In Section II, this paper examines the evolution of high speed scalability link. Electrical signaling is covered in section III, followed by a description of the complex internal/external topologies in Section IV. Link design challenges are examined in Section V. While Section VI covers modeling and simulation, Section VII addresses testing and validation. Future directions are discussed in section VIII and results are summarized in Section IX.

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Transmitter and channel equalization for high-speed server interconnects

Cited by 15 publications

References 1 publication

Analytical Eye-Diagram Determination for the Efficient and Accurate Signal Integrity Verification of Single Interconnect Lines

Analytical Eye-Diagram Determination for the Efficient and Accurate Signal Integrity Verification of Single Interconnect Lines

Analytical Eye-Diagram Determination for the Efficient and Accurate Signal Integrity Verification of Coupled Interconnect Lines

Complex high speed links in server environments

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