Transposed-Memory Free Implementation for Cost-Effective 2D-DCT Processor

Hsia, Shih-Chang; Tsai, Chin‐Feng; Wang, Szu-Hong; Hung, King-Chü

doi:10.1007/s11265-009-0344-5

Cited by 6 publications

(2 citation statements)

References 16 publications

(54 reference statements)

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“…By doing so, the 8-point 2-D DCT is decomposed into two 4x4 matrices which are multiplied by 4x1 vectors in a pipelined manner. Hsia [18] eliminated the use of transpose buffer by adopting a particular Since the IEEE-1180 conformance test is mainly intended for the IDCT computation, we also used the popular objective quality metric called Peak Signal to Noise Ratio (PSNR) to test and compare the FDCT quality of three different algorithms: LibJPEG LLM-based implementation, original Massimino's algorithm, and our modified version of Massimino's algorithm. The PSNR flowchart is shown in Figure 9, and works as follows.…”

Section: Review Of Related Workmentioning

confidence: 99%

Evaluating the Impact of Architectural Decisions on the Energy Efficiency of FDCT/IDCT Configurable IP Cores

Livramento

Moraes²,

Machado³

et al. 2020

JICS

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The development of mobile multimedia devices follows the platform-based design methodology in which IP cores are the building blocks. In the context of mobile devices there is a concern of battery lifetime which leads to the need of energy-efficient IP cores. This paper presents four energy-efficient FDCT/IDCT configurable IP cores. These architectures are based on Massimino’s algorithm, which was chosen due to its high accuracy and parallelism. The four architectures were built by combining fully-combinational or pipelined datapaths, using either a single or two 1-D DCT blocks with a transpose buffer that assures the optimal minimum latency of eight cycles. Synthesis results for 90nm showed that our most efficient architecture, which uses two pipelined 1-D blocks, achieved 250 MHz as maximum frequency at a total power of 14.03 mW. Such frequency was enough to process 16x 1080p@30fps videos in real time (nearly 2 GigaPixels/s). Comparisons with related work, in terms of energy efficiency (μJ/MPixels), revealed that our most energy-efficient architecture is at least 2 times as efficient as other DCT architectures. Moreover, the four designed architectures were also synthesized by using common low-power techniques. These results showed that pipelined versions at high throughput tend to take more benefit from using Low-Vdd and High-Vt combined than the combinational ones, thus becoming the most energy efficient.

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Section: Review Of Related Workmentioning

confidence: 99%

Evaluating the Impact of Architectural Decisions on the Energy Efficiency of FDCT/IDCT Configurable IP Cores

Livramento

Moraes²,

Machado³

et al. 2020

JICS

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“…We observed a tremendous increase in throughput compared to previously published results. The proposed memory subsystem also allows a latency time of just 8 clock cycles for DCT and IDCT compared to 22 cycles in [3] and 10 cycles in [4] while supporting slightly higher operating frequencies as well. The ASIC implementation too will provide peak throughput almost twice that observed in the earlier implementation.…”

Section: Implementation Of Signal Processing Algorithmsmentioning

confidence: 99%

Low latency transpose memory for high throughput signal processing

El-Hadedy

Purohit

Margala

et al. 2010

Proceedings of the 8th IEEE International NEWCAS Conference 2010

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This paper presents the design and analysis of a power and area efficient, low latency transpose memory structure for use in adaptive signal processing systems. The proposed architecture achieves significant improvements in system throughput over competing designs. We demonstrate the throughput performance of the proposed memory on FPGA as well as ASIC implementations. The memory was employed in a watermarking architecture previously proposed. The new memory design allows for 2X speed up in performance for the watermarking algorithm and up to 10X speedup for 2D DCT and IDCT algorithms compared to previously published work, while consuming significantly lower power and area.

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