2016
DOI: 10.1063/1.4963740
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Trap behaviours characterization of AlGaN/GaN high electron mobility transistors by room-temperature transient capacitance measurement

Abstract: In this paper, the trap behaviours in AlGaN/GaN high electron mobility transistors (HEMTs) are investigated using transient capacitance measurement. By measuring the transient gate capacitance variance (ΔC) with different pulse height, the gate pulse induced trap behaviours in SiNX gate dielectric layer or at the SiNX/AlGaN interface is revealed. Based on the results, a model on electron traps in AlGaN/GaN HEMTs is proposed. The threshold voltage (Vth) instability in AlGaN/GaN HEMTs is believed to be correlate… Show more

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Cited by 12 publications
(4 citation statements)
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“…30 At the beginning of cooling, most of activated pre-existing traps were de-activated, the electrons captured by the traps at the SiN X /GaN interface and in the barrier injected back to channel, which counterbalanced the influence of nitrogen vacancy defects on V th and then resulted in the V th moving in negative direction. As the temperature is further reduced, more electrons moved back to channel and the nitrogen vacancy defect mechanism dominated the V th moving toward the positive direction once again.…”
Section: Resultsmentioning
confidence: 99%
“…30 At the beginning of cooling, most of activated pre-existing traps were de-activated, the electrons captured by the traps at the SiN X /GaN interface and in the barrier injected back to channel, which counterbalanced the influence of nitrogen vacancy defects on V th and then resulted in the V th moving in negative direction. As the temperature is further reduced, more electrons moved back to channel and the nitrogen vacancy defect mechanism dominated the V th moving toward the positive direction once again.…”
Section: Resultsmentioning
confidence: 99%
“…The basic theory of pulsed stress has been reported in early publications. 29,30) The decay time comparison of the two heating mode at the same heating power (temperature) are shown in Fig. 4(b).…”
Section: Applied Physics Expressmentioning
confidence: 99%
“…[1] Generally, the trapping effect in an MIS gate stack could be related to traps at or near the interface, named interface states/border traps, or in the bulk of the insulator. [2,3] To date, various technologies have been employed to suppress threshold voltage (𝑉 th ) shift, including pre-fluorination argon treatment, [4] sputter deposited Al 2 O 3 , [5] and in situ dielectric predeposition plasma nitridation, [6] to reduce the trapping effect at/near the insulator/semiconductor interface. Due to the low deposition temperature, traps occur in high densities in the bulk gate insulators deposited by PECVD or ALD.…”
mentioning
confidence: 99%