This paper proposes an architecture for reconfigurable receivers that can operate in both Low-and Zero-IF modes. The hardware reuse is maximized by a newly proposed reconfigurable ∆ /Σ-∆modulator for data conversion. A new approach to the design of second order approximation for derivate computation in ∆ converter is also introduced. Simulation results shows the possibility to achieve data conversion at -70dB SQNR in Σ-∆ mode and -55dB in ∆ mode.