Tri-Level Resistive Switching in Metal-Nanocrystal-Based $\hbox{Al}_{2}\hbox{O}_{3}/\hbox{SiO}_{2}$ Gate Stack

Abstract

Abstract-Tri-level resistive switching behavior was observed in an Al 2 O 3 /SiO 2 gate stack with Ru metal nanocrystals embedded in the Al 2 O 3 layer. The device was successfully switched among three resistance states (high, medium, and low) after a forming process using a simple electrical method. The resistance ratio of the high-resistance state to the low-resistance state is more than 10 3 . The insulator-to-conductor (and vice versa) transition of the Al 2 O 3 and SiO 2 dielectric layers is elucidated by a physical model, which invokes oxygen ion (O 2− ) trapping/detrapping at the metal-oxide interfaces, as well as O 2− transport and annihilation with the oxygen vacancies in the breakdown percolation path. The switching transition of each individual dielectric layer is found to be dependent on the polarity of the gate bias. This new understanding opens the prospect of metal-nanocrystalbased Al 2 O 3 /SiO 2 gate stacks for a resistive switching memory application.Index Terms-Dielectric breakdown, metal nanocrystal (MNC), percolation path, resistive switching.

Complementary Resistive Switching in ZnO/Al2O3 Bi-Layer Devices

“…Two significant mechanisms associated with filament formation are; valance change memory (VCM) [34] and electrochemical metallization memory (ECM) based switching. As the electrodes used in the proposed device are inert (Au and FTO) [35]- [37], and the active layers are well-known oxides switching with oxygen vacancies, the possibility of ECMbased switching is ruled out. Also, in our study, the influence of protons or moisture on switching is not considered [38].…”

“…10(a). Then, as the input sweep reaches -0.8 V, the oxygen vacancies migrate toward the top electrode to form filament in the ZnO layer [37]; thereby, the device enters an LRS/LRS state or completely ON-state shown in Fig. 10(b).…”

Statistical characterization and reliability modeling of novel high-K gate dielectric stacks

“…5.9, after a negative sweep induced recovery (shown in Fig. 5.10(a)) can be clearly seen for all the gate stacks implying the possibility of O 2ion drift back to passivate the percolation path during the opposite polarity voltage sweep [269]. The trends also reveal that recovery is very minor for poly-Si gated stacks while moderate recovery is seen in NiSi and TaN stacks.…”