The parity generators and the checkers are the most important circuits in communication systems. With the development of multi-valued logic (MVL), the proposed system with parity generators and checkers is the most required using the recently developed optoelectronic technology in the modified trinary number (MTN) system. This system also meets up the tremendous needs of speeds by exploiting the savart plates and spatial light modulators (SLM) in the optical tree architecture (OTA).The modified trinary number (MTN) system finds its importance because of its carry and borrow free arithmetic operations [1][2][3] . Moreover, the basic logic gates are also possible to be implemented by using the spatial light modulator (SLM) and savart plate, exploiting the advantages of optics and optoelectronics [4][5][6] in the optical tree architecture (OTA). The modified signed-digit (MSD) number system is an extension of the base-2 system for the representation of both positive and negative numbers and capable of carry-free addition and borrow-free subtraction operations. This number representation system in trinary is called as the modified trinary number (MTN) system [7] and leads to higher information density.The parity bit/trit play the most important role in the verification of information transmission. The parity generator and checker have a lot of applications in communications. To implement them in the MTN system, different logical states and the implementation of different logic gates [7][8][9][10][11] are introduced here.In the MTN system, rather than two states in the case of binary logic, three distinct states to represent 1, 0 and 1 _ must be generated. The logical formulation is based on the definition of 1, 0 and 1 _ as