Triple-self-aligned, planar double-gate MOSFETs: devices and circuits

Guarini, K.W.; Solomon, P. M.; Zhang, Y.; Chan, K.; Jones, E.C.; Cohen, Guy; Krasnoperova, Azalia A.; Ronay, Maria; Dokumaci, O.; Bucchignano, J.; Cabral, C.; Lavoie, C.; Ku, V.; Boyd, D.; Petrarca, K.; Babich, I.; Treichler, J.; Kozlowski, P.; Newbury, J.; D'Emic, C.; Sicina, R.M.; Wong, Helen

doi:10.1109/iedm.2001.979527

Cited by 50 publications

(21 citation statements)

References 5 publications

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“…Because of improved electrostatics control, multiple-gate transistors allow for a triple drive current with respect to a single gate at a given off-state current [38]. Planar double gate MOSFETs have the potential to augment existing design libraries [39][40][41].…”

Section: Multigate Devicesmentioning

confidence: 98%

Ultra-thin films and multigate devices architectures for future CMOS scaling

Deleonibus

2011

Sci. China Inf. Sci.

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The nanoelectronics industry is facing historical challenges to scale down CMOS devices to meet demands for low voltage, low power, high performance and increased functionality. Using new materials and devices architectures is necessary. HiK gate dielectrics and metal gates have been introduced and have shown their ability to reduce power consumption. Fully depleted ultra-thin SOI devices are a good alternative to bulk for low power applications. Multigate devices are the current goal in device architecture to increase MOSFET drivability, reduce power, and allow new opportunities for future applications. Thin film based solutions will be necessary in the future because of fundamental limitations on gate capacitance scaling and system integration requirements. Exploiting 3D device stacking via wafer bonding could be a good way to introduce new materials (HiK, strained Si, hybrid orientations, Ge, III-Vs, Carbon-based materials, graphene and CNTs, and functional molecules) and continue increasing integration density. Si based CMOS will be scaled beyond the ITRS as the System-on-Chip/Wafer Platform.The international technology roadmap of semiconductors (ITRS) [1] distinguishes three types of products: high performance (HP), low operating power (LOP) and low standby power (LSTP) devices. In the HP case, a landmark has been reached at the 32-nm node: the contribution from static power dissipation approaches the dynamic power contribution [2]. Multigate devices could improve this somewhat by increasing the saturation current to leakage current ratio.In this review, we will first analyze the primary limitations and showstoppers of CMOS scaling. Issues on gate stack, channel and source and drain engineering as well as new device architectures (FDSOI or multigate devices) are discussed.Low power consumption and heterogeneous function integration will be leveraged by future nomadic systems. The increased number of devices and different types of signals will, in turn, require the leveraging of 3D IN package or ON chip co-integration. Limitations, showstoppers and opportunities of Si CMOS scalingCMOS device engineering consists of minimizing leakage current and the maximization of output current. In sub-100-nm CMOS devices, non-stationary transport is more important than diffusive transport. To this end, several questions arise related to the origins of the leakage currents, non-stationary transport limitations and supply voltage scaling.

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Section: Multigate Devicesmentioning

confidence: 98%

Ultra-thin films and multigate devices architectures for future CMOS scaling

Deleonibus

2011

Sci. China Inf. Sci.

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“…However, another major challenge is in the fabrication process, particularly for those structures requiring alignment of the top-and bottom-gate electrodes. The independently switched double-gate (ground-plane) structure [87,88] is similar to the tied double-gate planar structure, except that the top-and bottom-gate electrodes are electrically isolated to provide for independent biasing of the two gates. The top gate is typically used to switch the transistor ON and OFF, while the bottom gate is used for dynamic (or static) V th adjustment.…”

Section: Double-gate Mosfetmentioning

confidence: 99%

“…For these analytical expressions of the drain current, terminal charges and capacitances for the long-channel DG MOSFETs are obtained continuously in all operation regions, such as linear, saturation, and subthreshold. The drain current model, charge model, transconductance model, and capacitive model for symmetrical and asymmetrical DG MOSFETs are also developed in [88].…”

Section: Double-gate Mosfetmentioning

confidence: 99%

Introduction

Srivastava

Singh

2013

Analog Circuits and Signal Processing

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“…Candidates for such threedimensional devices are transistors with multiple gates such as FinFETs or Triple-Gate MOSFETs, usually fabricated on silicon-on-insulator (SOI) substrates [2][3][4][5]. SOI technology for multi-gate CMOS, however, results in a three-dimensional topography and therefore imposes new challenges for reactive ion etch (RIE) processes.…”

Section: Introductionmentioning

confidence: 99%