Trireme: Exploration of Hierarchical Multi-level Parallelism for Hardware Acceleration

Abstract

The design of heterogeneous systems that include domain specific accelerators is a challenging and time-consuming process. While taking into account area constraints, designers must decide which parts of an application to accelerate in hardware and which to leave in software. Moreover, applications in domains such as Extended Reality (XR) offer opportunities for various forms of parallel execution, including loop level, task level and pipeline parallelism. To assist the design process and expose every possible level of parallelism, we present Trireme , a fully automated tool-chain that explores multiple levels of parallelism and produces domain specific accelerator designs and configurations that maximize performance, given an area budget. FPGA SoCs were used as target platforms and Catapult HLS [7] was used to synthesize RTL using a commercial 12nm FinFET technology. Experiments on demanding benchmarks from the XR domain revealed a speedup of up to 20 ×, as well as a speedup of up to 37 × for smaller applications, compared to software-only implementations.

A Hardware Realization Framework for Fuzzy Inference System Optimization

“…To optimize hardware through its high-level description, a range of optimization techniques can be employed across different levels of granularity, from coarse-grained levels such as task graphs to fine-grained levels such as data flow graphs [19,20]. Computer arithmetic provides a suite of efficient methods and tools for minimizing the processing requirements of specific tasks, particularly at the fine-grained level [21][22][23].…”