True Random Number Generation using Latency Variations of Commercial MRAM Chips

Ferdaus, Farah; Talukder, B. M. S. Bahar; Sadi, Mehdi; Rahman, Tauhidur

doi:10.1109/isqed51717.2021.9424346

Cited by 14 publications

(8 citation statements)

References 30 publications

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“…Due to the experimental setup limitations, we are incapable of reducing the t W value any further. At t W = 2.5ns, the total number of failed bit count falls within 25.59% − 37.30%, which is sufficient for TRNG or PUF analysis [35] but not suitable for data approximation. However, at t W = 5ns and 10ns, the obtained total failed bits are almost negligible (< 5% and < 1%, respectively) for all ten chips.…”

Section: Selection Of T Wmentioning

confidence: 98%

“…Appropriate reduced time selection is essential for obtaining the most favorable trade-off between application quality and power savings. Towards this end, the experimental results reveal that some of the memory cells provide erroneous outputs if the data is written at the reduced timing parameters [35]. The number of these error-prone cells varies within the write pulse activation time range t = [0, t W ].…”

Section: Appropriate Reduced Time Selectionmentioning

confidence: 99%

See 1 more Smart Citation

Approximate MRAM: High-performance and Power-efficient Computing with MRAM Chips for Error-tolerant Applications

Ferdaus,

Talukder,

Rahman

2021

Preprint

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Approximate computing (AC) leverages the inherent error resilience and is used in many big-data applications from various domains such as multimedia, computer vision, signal processing, and machine learning to improve systems performance and power consumption. Like many other approximate circuits and algorithms, the memory subsystem can also be used to enhance performance and save power significantly. This paper proposes an efficient and effective systematic methodology to construct an approximate non-volatile magneto-resistive RAM (MRAM) framework using consumer-off-the-shelf (COTS) MRAM chips. In the proposed scheme, an extensive experimental characterization of memory errors is performed by manipulating the write latency of MRAM chips which exploits the inherent (intrinsic/extrinsic process variation) stochastic switching behavior of magnetic tunnel junctions (MTJs). The experimental results and error-resilient image application reveal that the proposed AC framework provides a significant performance improvement and demonstrates a maximum reduction in MRAM write current of ∼66% on average with negligible or no loss in output quality.

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Section: Selection Of T Wmentioning

confidence: 98%

Section: Appropriate Reduced Time Selectionmentioning

confidence: 99%

Approximate MRAM: High-performance and Power-efficient Computing with MRAM Chips for Error-tolerant Applications

Ferdaus,

Talukder,

Rahman

2021

Preprint

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“…3a) and t Reset,256 (Fig. 3b) as a function of different stress levels (up to maximum possible rewrite operations 5 ) over the 2K random address space. Fig.…”

Section: B Cell Characterizationmentioning

confidence: 99%

“…Therefore, classical security solutions that are elegant and reliable consume a significant amount of energy and can be vulnerable to physical attacks such as radiation and exposure to high temperatures [1]- [3]. However, emerging technology-based devices can provide new and robust security primitives and protocols that are potentially stronger than conventional, complementary metal oxide semiconductor (CMOS) device-based security solutions [4], [5]. These emerging devices have inherent process variations and exhibit nonlinear input-output relationships.…”

Section: Introductionmentioning

confidence: 99%

Approximate MRAM: High-performance and Power-efficient Computing with MRAM Chips for Error-tolerant Applications

Ferdaus

Talukder

Rahman

2022

IEEE Trans. Comput.

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This article introduces a novel, low-cost technique for hiding data in commercially available resistive-RAM (ReRAM) chips. The data is kept hidden in ReRAM cells by manipulating its analog physical properties through switching (set/reset) operations. This hidden data, later, is retrieved by sensing the changes in cells' physical properties (i.e., set/reset time of the memory cells). The proposed system-level hiding technique does not affect the normal memory operations and does not require any hardware modifications. Furthermore, the proposed hiding approach is robust against temperature variations and the aging of the devices through normal read/write operation. The silicon results show that our proposed data hiding technique is acceptably fast with ∼0.4bit/min of encoding and ∼15.625bits/s of retrieval rates, and the hidden message is unrecoverable without the knowledge of the secret key, which is used to enhance the security of hidden information.

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“…However, the new approaches unified the TRNG with the memories used in the system, reducing the area overhead. The unified TRNG uses the different physical phenomena to generate random sequence with the undesirable effects in the Static memory (SRAM) [31], [32], Dynamic memory (DRAM) [33], [34], Resistive memory (RRAM) [35]- [38], Magnetic memory (MRAM) [39], [40]. An NVRAM with the control gate methodology can be used for TRNG applications, reading the noise while sensing their threshold voltage [10].…”

Section: Introductionmentioning

confidence: 99%