Truncated Online Arithmetic with Applications to Communication Systems

Rajagopal, Sridhar; Cavallaro, Joseph R.

doi:10.1109/tc.2006.168

Cited by 9 publications

(1 citation statement)

References 33 publications

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“…Redundant algorithm-based carry-free addition has attracted numerous attention due to its enhanced performance as compared with other adders, including faster speed and fixed delay irrespective of adder depth 14,15 . Unlike traditional least-significant-bit-first (LSBF) addition methods, carry-free adders (CFAs) facilitate most-significant-bit-first (MSBF) computations, thereby enabling arithmetic operations of arbitrary precision 16 .…”

Section: Introductionmentioning

confidence: 99%

Carry-Free Adder in Redundant Number System: the First and Only Demonstration of Ternary Logic’s Superiority Over Binary Logic

Huang,

Zhao,

et al. 2024

Preprint

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Ternary logic has attracted significant attention due to its higher data density and balanced number representation. Even though tremendous endeavor has been devoted to developing ternary logic arithmetic circuits with compact structures, its industrial applications have stagnated for years due to the inferior energy efficiency compared to binary systems. In this work, we introduce various carry-free arithmetic circuit designs based on ternary logic and redundant number systems (RNS). For the first time, our proposed ternary arithmetic circuits outperform their binary counterparts with equivalent computation capabilities in energy efficiency across various data widths. Various arithmetic circuits including mixed adders, mixed subtractors, and signed adders were designed and implemented. Comprehensive simulations of the proposed 4/8/12/16/32-bit arithmetic circuits were performed using the SMIC180 process design kit (PDK), which demonstrated significant performance advances over the existing binary logic-based circuits. Specifically, our 8-bit carry-free mixed adders and subtractors show reductions in power consumption by 35.5% and 40.8% respectively, operating at 200 MHz. Furthermore, our carry-free signed adders exhibit superior speed and double the operational frequency (200 vs. 100 MHz). When benchmarked against the binary approaches at the binary frequency limit, our circuits reduce the power consumption by 10.22%. These results not only demonstrate the great potential of our approach in broader computational applications but also shed insights into the energy-efficient, high-speed arithmetic circuit design based on ternary logic.

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Section: Introductionmentioning

confidence: 99%