Trunking of TDM and narrowband services over IP Networks

Aweya, James

doi:10.1002/nem.458

Cited by 11 publications

(6 citation statements)

References 18 publications

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“…Detailed network statistics are given in Table I. Note CES applications typically demand well-controlled networks where network jitter, packets losses and other network impairments are kept very low [2].…”

Section: Receiver Pll Implementation Using a Vcomentioning

confidence: 99%

Clock synchronization for packet networks using a weighted least‐squares error filtering technique and enabling circuit emulation service

Aweya

Montuno

Ouellette

et al. 2006

Int J Communication

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SUMMARYCircuit emulation service (CES) allows time-division multiplexing (TDM) services (T1/E1 and T3/E3 circuits) to be transparently extended across a packet network. With circuit emulation over IP, for instance, TDM data received from an external device at the edge of an IP network is converted to IP packets, sent through the IP network, passed out of the IP network to its destination, and reassembled into TDM bit stream. Clock synchronization is very important for CES. This paper presents a clock synchronization scheme based on a double exponential filtering technique and a linear process model. The linear process model is used to describe the behaviour of clock synchronization errors between a transmitter and a receiver. In the clock synchronization scheme, the transmitter periodically sends explicit time indications or timestamps to a receiver to enable the receiver to synchronize its local clock to the transmitter's clock. A phase-locked loop (PLL) at the receiver processes the transmitted timestamps to generate timing signal for the receiver. The PLL has a simple implementation and provides both fast responsiveness (i.e. fast acquisition of transmitter frequency at a receiver) and significant jitter reduction in the locked state.

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Section: Receiver Pll Implementation Using a Vcomentioning

confidence: 99%

Clock synchronization for packet networks using a weighted least‐squares error filtering technique and enabling circuit emulation service

Aweya

Montuno

Ouellette

et al. 2006

Int J Communication

Self Cite

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show abstract

“…Note CES applications typically demand wellcontrolled networks where network jitter, packets losses and other network impairments are kept very low. 2 A software tool was developed to generate the network jitter statistics and then simulate the clock synchronization scheme. In Figure 12, the transmitter is configured with a frequency offset of 0 ppm (from the nominal).…”

Section: Simulation Studiesmentioning

confidence: 99%

“…[1][2][3][4] For example, to interwork circuit-switched timedivision multiplexing (TDM) networks whose services are predominantly time-sensitive through a packet switched network, the packet network must essentially behave as a transparent 'link' in the endto-end path between the TDM networks. This transparent inclusion of a packet network in an end-toend path of a connection that carries circuit-switched time-sensitive or TDM services is referred to as 'circuit emulation' on the packet network.…”

Section: Introductionmentioning

confidence: 99%

Clock synchronization using a linear process model

et al. 2005

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SUMMARYIn this paper, we present a clock synchronization scheme based on a simple linear process model which describes the behaviors of clocks at a transmitter and a receiver. In the clock synchronization scheme, a transmitter sends explicit time indications or timestamps to a receiver, which uses them to synchronize its local clock to that of the transmitter. Here, it is assumed that there is no common network clock available to the transmitter and the receiver and, instead, the receiver relies on locking its clock to the arrival of the timestamps sent by the transmitter. The clock synchronization algorithm used by the receiver is based on a weighted least-squares criterion. Using this algorithm, the receiver observes and processes several consecutive clock samples (timestamps) to generate accurate timing signals. This algorithm is very efficient computationally, and requires the storage of only a small number of clock samples in order to generate accurate timing signals.

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“…Circuit emulation for time division multiplexing (TDM) traffic over packet networks is receiving much attention nowadays [1][2][3][4]. A packet network that interconnects TDM devices must essentially behave as a transparent 'link' in the end-to-end TDM connection.…”

Section: Introductionmentioning

confidence: 99%

Analysis of a clock‐recovery technique for circuit emulation services over packet networks

Aweya

Montuno

Ouellette

et al. 2007

Int J Communication

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SUMMARYOne important requirement of circuit emulation services (CES) over packet networks is clock synchronization and timing distribution among the nodes. CES depends on reliable and high-quality timing for operations. In the time division multiplexing (TDM) world, whether plesiochronous digital hierarchy (PDH), synchronous digital hierarchy (SDH) or synchronous optical network (SONET) based, timing and synchronization is inherent in the design of the network. However, when timing critical services such PDH and SDH/SONET are carried over packet network (e.g. IP, Ethernet, etc.), the timing element is lost and has to be carried across the packet network by other means. A well-known and widely implemented technique for clock recovery in CES is one that is based on packet inter-arrival time (sometimes called time difference of arrival) averaging. The technique is very simple to implement but provides good performance only when packet losses and packet delay variation (PDV) are very low and well controlled. This technique has been extensively analysed through simulations but has not been fully characterized analytically with correlated traffic in the literature. In this paper, we provide a full analytical examination of this well-known clock recovery technique. We analyse the effects of correlation of the delay variation in the traffic stream on the quality of the clock recovered by a receiver. We prove analytically that, for a general input process, high correlation of the delay variation produces a large variance of the recovered clock.

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Trunking of TDM and narrowband services over IP Networks

Cited by 11 publications

References 18 publications

Clock synchronization for packet networks using a weighted least‐squares error filtering technique and enabling circuit emulation service

Clock synchronization for packet networks using a weighted least‐squares error filtering technique and enabling circuit emulation service

Clock synchronization using a linear process model

Analysis of a clock‐recovery technique for circuit emulation services over packet networks

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