TSV Replacement and Shield Insertion for TSV–TSV Coupling Reduction in 3-D Global Placement

Abstract

Through silicon via (TSV) cross coupling can seriously degrade circuit performance of 3-D ICs if it is not considered during design. In this paper, we propose two algorithms which combine coupling-aware TSV placement with shield insertion to yield better results than either technique alone. We first introduce an algorithm for TSV placement assuming a fixed standard cell placement. The result of this algorithm is a 13% reduction in worst case coupling across all TSV pairs and a 90% reduction in the total number of TSV pairs violating an imposed coupling threshold. We then introduce a second algorithm that perturbs a given standard cell and TSV placement to improve coupling. This second algorithm yields a 17% reduction in worst case coupling and removes all coupling violations. Both algorithms cause wirelength (WL) to increase no more than 5%. Our algorithms offer a large improvement to TSV-TSV coupling at the expense of only a meager degradation of total WL, and in many designs and applications this trade-off is well justified.

Early Layout Design Exploration in TSV-based 3D Integrated Circuits

“…Several prior works [57][58][59][60][61][62][63][64] have analyzed coupling noise in 3D interconnects due to big-size TSVs. These studies focus on the placement stage, where the relative position of blocks and TSVs is fixed.…”

“…As can be observed from Figure 38(a) & (b), the proposed detail assignment further reduces coupling noise by 22% and 25% for n200 and n300 circuits respectively.The significant reduction in coupling noise due to detail nets-to-TSVs assignment shows that early floorplanning and careful nets-to-TSVs assignment can be critical for overall design convergence and timely sign-off. This approach overcomes the limitations associated with the post-layout planning techniques focusing solely on the minimization of TSV-to-TSV coupling[57][58][59][60][61][62][63][64]. Performing detail assignment further fine-tunes the noise performance of the final floorplan, providing greater insight towards making better design decisions up front, so that overall design convergence and timing closure can be better achieved.…”