Tunable Floating-Point Adder

Nannarelli, Alberto

doi:10.1109/tc.2019.2906907

Cited by 17 publications

(3 citation statements)

References 8 publications

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“…Nannarelli [18] describes the design of an FPU based on the Tunable Floating-Point (TFP) format, which supports a variable number of bits for mantissa (from 4 to 24) and exponent (from 5 to 8). However, this solution does not support vectorization, which is a key enabler for energy efficiency.…”

Section: Transprecision Computing Building Blocksmentioning

confidence: 99%

A Low-Power Transprecision Floating-Point Cluster for Efficient Near-Sensor Data Analytics

Montagna

Mach

Benatti

et al. 2022

IEEE Trans. Parallel Distrib. Syst.

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Recent applications in low-power (1-20 mW) near-sensor computing require the adoption of floating-point arithmetic to reconcile high precision results with a wide dynamic range. In this paper, we propose a low-power multi-core computing cluster that leverages the fined-grained tunable principles of transprecision computing to provide support to near-sensor applications at a minimum power budget. Our solution -based on the open-source RISC-V architecture -combines parallelization and sub-word vectorization with a dedicated interconnect design capable of sharing floating-point units (FPUs) among the cores. On top of this architecture, we provide a full-fledged software stack support, including a parallel low-level runtime, a compilation toolchain, and a high-level programming model, with the aim to support the development of end-to-end applications. We performed an exhaustive exploration of the design space of the transprecision cluster on a cycle-accurate FPGA emulator, varying the number of cores and FPUs to maximize performance. Orthogonally, we performed a vertical exploration to identify the most efficient solutions in terms of non-functional requirements (operating frequency, power, and area). We conducted an experimental assessment on a set of benchmarks representative of the near-sensor processing domain, complementing the timing results with a post place-&-route analysis of the power consumption. A comparison with the state-of-the-art shows that our solution outperforms the competitors in energy efficiency, reaching a peak of 97 Gflop/s/W on single-precision scalars and 162 Gflop/s/W on half-precision vectors. Finally, a real-life use case demonstrates the effectiveness of our approach in fulfilling accuracy constraints.

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Section: Transprecision Computing Building Blocksmentioning

confidence: 99%

A Low-Power Transprecision Floating-Point Cluster for Efficient Near-Sensor Data Analytics

Montagna

Mach

Benatti

et al. 2022

IEEE Trans. Parallel Distrib. Syst.

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“…In [24], the suggested adder is Tunable Floating Point (TFP) where the specific number of bits for substantial and exponent in the floating point illustration, in which the power efficient is calculated. The pair of circuit is used in the application of ternary half adder [25] with the improvement of multi-level ternary and basic binary circuits in which one path diminishes the computational resource through the power delay of about 63%.…”

Section: Introductionmentioning

confidence: 99%

Performance Measurement of Energy Efficient and Highly Scalable Hybrid Adder

Annapoorani¹,

Marikkannu²

2023

Computer Systems Science and Engineering

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The adders are the vital arithmetic operation for any arithmetic operations like multiplication, subtraction, and division. Binary number additions are performed by the digital circuit known as the adder. In VLSI (Very Large Scale Integration), the full adder is a basic component as it plays a major role in designing the integrated circuits applications. To minimize the power, various adder designs are implemented and each implemented designs undergo defined drawbacks. The designed adder requires high power when the driving capability is perfect and requires low power when the delay occurred is more. To overcome such issues and to obtain better performance, a novel parallel adder is proposed. The design of adder is initiated with 1 bit and has been extended up to 32 bits so as verify its scalability. This proposed novel parallel adder is attained from the carry look-ahead adder. The merits of this suggested adder are better speed, power consumption and delay, and the capability in driving. Thus designed adders are verified for different supply, delay, power, leakage and its performance is found to be superior to competitive Manchester Carry Chain Adder (MCCA), Carry Look Ahead Adder (CLAA), Carry Select Adder (CSLA), Carry Select Adder (CSA) and other adders.

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“…FPA has various operations of variable latencies and the latency of FPA should be be optimized [13,14]; either by determining the smaller exponent to be subtracted from the larger exponent [15], or by using dual path algorithm [16][17][18][19][20][21][22], or considering subtraction operation separately [23]. Various design techniques are proposed to improve the performance of FPA to increase its speed [24][25][26][27][28], to reduce its silicon area [29], dealing with denormalized numbers [30] and rounding logic [31] and implementing FPA using field programmable gate array (FPGA) [32,33]. A Leading Zero Anticipator (LZA) is also designed for normalization process in dual path algorithm to improve the speed of FPA [34][35][36][37][38], and extensive research articles are available for synchronous FPA [39][40][41][42][43][44][45].…”

Section: Introductionmentioning

confidence: 99%

Asynchronous Floating-Point Adders and Communication Protocols: A Survey

2020

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Addition is the key operation in digital systems, and floating-point adder (FPA) is frequently used for real number addition because floating-point representation provides a large dynamic range. Most of the existing FPA designs are synchronous and their activities are coordinated by clock signal(s). However, technology scaling has imposed several challenges like clock skew, clock distribution, etc., on synchronous design due to presence of clock signal(s). Asynchronous design is an alternate approach to eliminate these challenges imposed by the clock, as it replaces the global clock with handshaking signals and utilizes a communication protocol to indicate the completion of activities. Bundled data and dual-rail coding are the most common communication protocols used in asynchronous design. All existing asynchronous floating-point adder (AFPA) designs utilize dual-rail coding for completion detection, as it allows the circuit to acknowledge as soon as the computation is done; while bundled data and synchronous designs utilizing single-rail encoding will have to wait for the worst-case delay irrespective of the actual completion time. This paper reviews all the existing AFPA designs and examines the effects of the selected communication protocol on its performance. It also discusses the probable outcome of AFPA designed using protocols other than dual-rail coding.

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Tunable Floating-Point Adder

Cited by 17 publications

References 8 publications

A Low-Power Transprecision Floating-Point Cluster for Efficient Near-Sensor Data Analytics

A Low-Power Transprecision Floating-Point Cluster for Efficient Near-Sensor Data Analytics

Performance Measurement of Energy Efficient and Highly Scalable Hybrid Adder

Asynchronous Floating-Point Adders and Communication Protocols: A Survey

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