Tuner Loop Based on FPGA for Petra Cavity at TPS Booster Ring

Abstract

The low-level radio frequency system of the Taiwan Photon Source, TPS, booster ring was replaced by the digital low-level RF system, DLLRF, in 2018. After that, the phase drift compensation loop for energy-saving operation and the tuner loop were also implemented in the DLLRF system sequentially. We used Altera-DE3 to build the core of DLLRF and handle the high-speed ADC/DAC procedure for RF signal sampling. As we con-sider the response time of the tuner, we choose an-other low-cost board, Altera-DE0-Nano, to develop the tuner loop for 5-Cell-Petra-Cavity. It has an eight-channel 12-bits-ADC, 150 ksps, ADC128S022, to detect the positions of two tuners and two transmitted powers sampled from two cells of the 5-Cell-Petra-Cavity for a power balance function. The phase information of for-ward power and cavity gap voltage will come from the Altera-DE3 to tell the tuner loop in the Altera-DE0-Nano whether the cavity is on resonance or not. The tuner loop controls the cavity to work not only at the resonance frequency but also with a balanced electric field distribution. This study presents the tuner loop’s architecture, including the locking resonance frequency and field balance functions. The performance of the field balance function is observed by the archive data of the two tuners positions and two transmit power signals.