Tuning the VSIDS decision heuristic for bounded model checking

Shacham, Ohad; Zarpas, Emmanuel

doi:10.1109/mtv.2003.1250266

Cited by 19 publications

(9 citation statements)

References 3 publications

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“…Using the extended version of Strategy 4, also merging ITE-trees with their AND/OR leaves with fanout count greater than 1-in order to shorten more paths from primary inputs to the Boolean circuit outputresulted in equal or better performance for 5 of the 10 benchmarks. Strategy "old best" was better than Strategy 4 on 4 of the buggy models, and Strategy 0 was better than Strategy 4 on 5 models, thus the potential for further speedups with parallel runs of the tool flow, each with different strategy, as used in [56] [68].…”

Section: Resultsmentioning

confidence: 99%

Exploiting signal unobservability for efficient translation to CNF in formal verification of microprocessors

Velev¹

Proceedings. Design, Automation and Test in Europe Conference and Exhibition

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The paper presents a method for translating Boolean circuits to CNF by identifying trees of ITE operators, where each ITE has fanout count of 1, and representing every such tree with a single set of equivalent CNF clauses without intermediate variables for ITE outputs, except for the tree output. This not only eliminates intermediate variables, but also reduces the number of clauses, compared to conventional translation to CNF, where each ITE is assigned an output variable and is represented with a separate set of clauses. Other gates with fanout count of 1 are similarly merged with their fanout gate to generate a single set of equivalent clauses. This translation to CNF was implemented in a decision procedure for the logic of Equality with Uninterpreted Functions and Memories (EUFM), and was applied to formulas from formal verification of microprocessors. To increase the number of ITE-trees in the Boolean formulas, the decision procedure was optimized to preserve the ITE-tree structure of arguments to equality comparisons. In conventional translation to CNF with the unoptimized decision procedure, the benchmark formulas require up to hundreds of thousands of CNF variables and millions of clauses. The best translation strategy reduced the CNF variables by up to 8×; the clauses by up to 17×; the SATsolver decisions by up to 79×; the SAT-solver conflicts by up to 96×; and accelerated the SAT solving by up to 420× .

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Section: Resultsmentioning

confidence: 99%

Exploiting signal unobservability for efficient translation to CNF in formal verification of microprocessors

Velev¹

Proceedings. Design, Automation and Test in Europe Conference and Exhibition

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“…He evaluated seven strategies on the Grasp SAT solver, and found that static ordering does perform fairly well, although no parameter combination was a clear winner. Later, Shacham and Zarpas [12] showed that Shtrichman's conclusions do not apply to zChaff's less greedy VSIDS heuristic on their set of benchmarks, claiming that Shtrichman's conclusions were either benchmark-or engine-dependent. Shacham and Zarpas evaluated four different decision strategies on IBM BMC instances, and found that static ordering performs worse than VSIDS-based strategies.…”

Section: Related Workmentioning

confidence: 99%

Boosting Verification by Automatic Tuning of Decision Procedures

Hutter

Babic

Hoos

et al. 2007

Formal Methods in Computer Aided Design (FMCAD'07)

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Abstract-Parameterized heuristics abound in computer aided design and verification, and manual tuning of the respective parameters is difficult and time-consuming. Very recent results from the artificial intelligence (AI) community suggest that this tuning process can be automated, and that doing so can lead to significant performance improvements; furthermore, automated parameter optimization can provide valuable guidance during the development of heuristic algorithms. In this paper, we study how such an AI approach can improve a state-of-theart SAT solver for large, real-world bounded model-checking and software verification instances. The resulting, automaticallyderived parameter settings yielded runtimes on average 4.5 times faster on bounded model checking instances and 500 times faster on software verification problems than extensive handtuning of the decision procedure. Furthermore, the availability of automatic tuning influenced the design of the solver, and the automatically-derived parameter settings provided a deeper insight into the properties of problem instances.

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“…However, recent results [88] show that the conflictdriven variable ordering heuristics used in modern SAT solvers (e.g., the VSIDS heuristic in zchaff [77]) outperform any fully static BMC-specific variable ordering scheme, such as the one proposed in [95]. A slight tuning of these heuristics for the BMC problem [88] can fur-ther enhance the performance.…”

Section: Decision Variable Ordering Of the Sat Solvermentioning

confidence: 99%

“…A slight tuning of these heuristics for the BMC problem [88] can fur-ther enhance the performance. On the other hand, BMC tools using circuit-based SAT solvers (e.g., [41,59,64]) essentially use some variant of the J-frontier justification heuristic popularly used in sequential ATPG tools.…”

Section: Decision Variable Ordering Of the Sat Solvermentioning

confidence: 99%

A survey of recent advances in SAT-based formal verification

Prasad

Biere

Gupta³

2005

Int J Softw Tools Technol Transfer

204

120

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Abstract. Dramatic improvements in SAT solver technology over the last decade and the growing need for more efficient and scalable verification solutions have fueled research in verification methods based on SAT solvers. This paper presents a survey of the latest developments in SAT-based formal verification, including incomplete methods such as bounded model checking and complete methods for model checking. We focus on how the surveyed techniques formulate the verification problem as a SAT problem and how they exploit crucial aspects of a SAT solver, such as application-specific heuristics and conflict-driven learning. Finally, we summarize the noteworthy achievements in this area so far and note the major challenges in making this technology more pervasive in industrial design verification flows.

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Tuning the VSIDS decision heuristic for bounded model checking

Cited by 19 publications

References 3 publications

Exploiting signal unobservability for efficient translation to CNF in formal verification of microprocessors

Exploiting signal unobservability for efficient translation to CNF in formal verification of microprocessors

Boosting Verification by Automatic Tuning of Decision Procedures

A survey of recent advances in SAT-based formal verification

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