Tunnel field-effect transistor charge-trapping memory with steep subthreshold slope and large memory window

Kino, Hisashi; Fukushima, T.; Tanaka, Tetsu

doi:10.7567/jjap.57.04fe07

Cited by 6 publications

(5 citation statements)

References 29 publications

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“…Within 1000 s of programming, some of the charges stored in the HfO 2 trap layer near the tunnelling layer were lost. 30 The charge concentrations in the HfO 2 trap layers near the tunnelling layers of Hf:Al 8:2 and Hf:Al 7:3 were less than that in Hf:Al 9:1. A small electron concentration causes less leakage, which promotes charge retention.…”

Section: Resultsmentioning

confidence: 89%

Improvement of the Charge Retention of a Non-Volatile Memory by a Bandgap-Engineered Charge Trap Layer

Cui

Xin

Kim

et al. 2021

ECS J. Solid State Sci. Technol.

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In recent years, research based on HfO2 as a charge trap memory has become increasingly popular. This material, with its advantages of moderate dielectric constant, good interface thermal stability and high charge trap density, is currently gaining in prominence in the next generation of nonvolatile memory devices. In this study, memory devices based on a-IGZO thin-film transistor (TFT) with HfO2/Al2O3/HfO2 charge trap layer (CTL) were fabricated using atomic layer deposition. The effect of the Al2O3 layer thickness (1, 2, and 3 nm) in the CTL on memory performance was studied. The results show that the device with a 2-nm Al2O3 layer in the CTL has a 2.47 V memory window for 12 V programming voltage. The use of the HfO2/Al2O3/HfO2 structure as a CTL lowered the concentration of electrons near the tunnel layer and the loss of trapped electrons. At room temperature, the memory window is expected to decrease by 0.61 V after 10 years. The large storage window (2.47 V) and good charge retention (75.6% in 10 years) of the device under low-voltage conditions are highly advantageous. The charge retention of the HfO2/Al2O3/HfO2 trap layer affords a feasible method for fabricating memory devices based on a-IGZO TFT.

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Section: Resultsmentioning

confidence: 89%

Improvement of the Charge Retention of a Non-Volatile Memory by a Bandgap-Engineered Charge Trap Layer

Cui

Xin

Kim

et al. 2021

ECS J. Solid State Sci. Technol.

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“…A non-volatile tunnel-FET memory consists of the MONOS and tunnel-FET structures [13]. This memory device has many advantages, such as low-voltage operation and small cell size.…”

Section: Generation Of Stdp With Non-volatile Tunnel-fet Memory For Lmentioning

confidence: 99%

“…Therefore, low-voltage synaptic devices are required to implement low-power large-scale SNNs. To reduce the operation voltage, we propose a non-volatile tunnel-FET memory [13], [18]. The proposed memory device consists of the MONOS and tunnel-FET structures.…”

Section: Non-volatile Tunnel Fet Memorymentioning

confidence: 99%

Generation of STDP With Non-Volatile Tunnel-FET Memory for Large-Scale and Low-Power Spiking Neural Networks

Kino

Fukushima

Tanaka

2020

IEEE J. Electron Devices Soc.

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Spiking neural networks (SNNs) have attracted considerable attention as next-generation neural networks. As SNNs consist of devices that have spike-timing-dependent plasticity (STDP) characteristics, STDP is one of the critical characteristics we need to consider to implement an SNN. In this study, we generated the STDP of a biological synapse with non-volatile tunnel-field-effect-transistor (tunnel FET) memory that has a charge-storage layer and a tunnel FET structure. Tunnel FET is a promising structure to reduce the operation voltage owing to its steep sub-threshold slope. Therefore, the non-volatile tunnel-FET memory we propose enables the implementation of low-operation-voltage SNNs. This paper reports the I-V, programing, and both symmetric and asymmetric STDP characteristics of a non-volatile tunnel-FET memory with p-channel-MOS-like operation.

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“…The TFET-based Flash memory cell exhibits a higher program/erase speed and higher programming efficiency as the cell gate length scales from 180 nm down to 45 nm [16]. Kino et al [17] proposed a structure combining the novel SONOS memory devices with the TFET structure for a larger memory window (MW) and lower-power operation. Han et al [18] presented TFET-based SONOS memory to achieve better off-state leakage current characteristics.…”

Section: Introductionmentioning

confidence: 99%

Numerical simulation of vertical tunnelling field-effect transistors charge-trapping memory with TCAD tools

Cao

Tian

Majumdar

et al. 2021

Semicond. Sci. Technol.

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A novel vertical tunnelling field-effect transistor (TFET) based on silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory device, named as VT-SONOS, is proposed and investigated using TCAD simulations. Different from traditional planar TFET-based SONOS memory, the VT-SONOS device is programmed via band-to-band tunnelling for vertical pocket and Fowler–Nordheim tunnelling for both pocket/bottom oxide (OXb) and channel/OXb regions, which leads to a steeper subthreshold swing (SS) and a larger on-state current (I ON). The device structure is constructed using Sentaurus TCAD tools, and I D–V G characteristics were extracted using TCAD tools. Obtained SS value is 102.09 mV dec−1, while the I ON was 3.02 × 10−4 A. The memory window was 2.95 V, showing more dependence on programming pulse height (V gp) than erasing pulse height (V ge). Furthermore, 10-year retention characteristics were studied to investigate critical reliability issue. About 60% of the initial trapped charges remained in the device after unbiased 3.15 × 108 s (10 years) storage.

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Tunnel field-effect transistor charge-trapping memory with steep subthreshold slope and large memory window

Cited by 6 publications

References 29 publications

Improvement of the Charge Retention of a Non-Volatile Memory by a Bandgap-Engineered Charge Trap Layer

Improvement of the Charge Retention of a Non-Volatile Memory by a Bandgap-Engineered Charge Trap Layer

Generation of STDP With Non-Volatile Tunnel-FET Memory for Large-Scale and Low-Power Spiking Neural Networks

Numerical simulation of vertical tunnelling field-effect transistors charge-trapping memory with TCAD tools

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