Tunnel Junction with Perpendicular Magnetic Anisotropy: Status and Challenges

Wang, Mengxing; Zhang, Yue; Xuan, Zhao; Zhao, Weisheng

doi:10.3390/mi6081023

Cited by 47 publications

(19 citation statements)

References 75 publications

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“…The switching current requirements of our device, important for energy efficiency, are notably set by the style of anisotropy in our output MTJ. For all the following simulations, we have assumed that the device has perpendicular magnetic anisotropy (PMA), which typically has a lower energy barrier and thus a reduced switching current compared with in-plane magnetic anisotropy (IMA) [25]. Table 1 lists the parameters used for the comparison of DW-MTJ logic with the 2018 CMOS technology node of the International Technology Roadmap for Semiconductors [26], which assumes a metal-1 half pitch of 15 nm.…”

Section: Dw-mtj Device and Adder Design A Dw-device And Its Varimentioning

confidence: 99%

Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder

Xiao

Marinella

Bennett

et al. 2019

IEEE J. Explor. Solid-State Comput. Devices Circuits

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The domain-wall (DW)-magnetic tunnel junction (MTJ) device implements universal Boolean logic in a manner that is naturally compact and cascadable. However, an evaluation of the energy efficiency of this emerging technology for standard logic applications is still lacking. In this article, we use a previously developed compact model to construct and benchmark a 32-bit adder entirely from DW-MTJ devices that communicates with DW-MTJ registers. The results of this large-scale design and simulation indicate that while the energy cost of systems driven by spin-transfer torque (STT) DW motion is significantly higher than previously predicted, the same concept using spin-orbit torque (SOT) switching benefits from an improvement in the energy per operation by multiple orders of magnitude, attaining competitive energy values relative to a comparable CMOS subprocessor component. This result clarifies the path toward practical implementations of an all-magnetic processor system. INDEX TERMS Benchmarking, domain wall (DW), magnetic logic, magnetic tunnel junction (MTJ), post-CMOS logic, spintronics.

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Section: Dw-mtj Device and Adder Design A Dw-device And Its Varimentioning

confidence: 99%

Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder

Xiao

Marinella

Bennett

et al. 2019

IEEE J. Explor. Solid-State Comput. Devices Circuits

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“…It can revolutionize the product performance in digital memories, particularly capable of substituting all current up-to-date memories like hard disk drives, random-access memories, and Flash memories. Among all the technology candidates, memristor-based ReRAM operates faster than phase change random access memory (PCRAM), and it possesses not a simpler, but a smaller cell structure than magnetic random access memory (MRAM) or shared transistor technology random access memory (STT-RAM) [ 3 , 4 , 5 ]. Confronted with a traditional Metal-Oxide-Semiconductor (MOS)-accessed memory cell, memristor-based RRAM bears the promising potential of forming a cross-point structure without access devices, for the sake of achieving an ultra-high density form of data storage.…”

Section: Introductionmentioning

confidence: 99%

Tunable Memristic Characteristics Based on Graphene Oxide Charge-Trap Memory

2019

Micromachines

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Solution-processable nonvolatile memory devices, consisted of graphene oxide (GO) embedded into an insulating polymer polymethyl methacrylate (PMMA), were manufactured. By varying the GO content in PMMA nanocomposite films, the memristic conductance behavior of the Ni/PMMA:GO/Indium tin oxide (ITO) sandwiched structure can be tuned in a controllable manner. An investigation was made on the memristic performance mechanism regarding GO charge-trap memory; these blends were further characterized by transmission electron microscope (TEM), scanning electron microscope (SEM), Fourier transform infrared spectra (FTIR), Raman spectra, thermogravimetric analysis, X-ray diffraction (XRD), ultraviolet-visible spectroscopy, and fluorescence spectra in particular. Dependent on the GO content, the resistive switching was originated from the charges trapped in GO, for which bipolar tunable memristic behaviors were observed. PMMA:GO composites possess an ideal capability for large area device applications with the benefits of superior electronic properties and easy chemical modification.

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“…TDDB is a mechanism to determine the MTJ lifetime and depends on the polarity of applied voltage, thickness variations, and other process induced damages [189]. pMTJ having an oxide barrier of size less than 1 nm designed to transmit a high-density spinpolarized current (>1 MA/cm 2 ) can cause dielectric breakdown due to self-heating, which can generate a functional error in the hybrid CMOS/MTJ circuits [117,190]. Wang et al proposed a compact model of MTJ by incorporating the phenomena of dielectric breakdown of the MgO barrier with STT stochastic behavior in which technical variations and temperature evaluation are integrated [36].…”

Section: A Brief History Of Mtj Device Modelingmentioning

confidence: 99%

From MTJ Device to Hybrid CMOS/MTJ Circuits: A Review

et al. 2020

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Spintronics is one of the growing research areas which has the capability to overcome the issues of static power dissipation and volatility suffered by the complementary metal-oxide-semiconductor (CMOS) industry. Magnetic tunnel junction (MTJ), one of the prominent spintronic devices, is not only used to develop the fully non-volatile-logic (NV-L) but combines magnetism and electronics to develop next-generation NVmemory (NV-M) and hybrid CMOS/MTJ circuits. To be specific towards hybrid CMOS/MTJ circuits, the fabrication of first hybrid full-adder in 2009, fabrication of MTJ based 240-tile NV-field programmable gate array (NV-FPGA) chip in 2013, fabrication of a 3000-6-input-LUTs based NV-FPGA chip in 2015, fabrication of MTJ based NV-logic-in-memory-large scale integration (NV-LIM-LSI) in 2017 and recently the fabrication of a full hybrid magnetic/CMOS System on Chip (SoC) under EU GREAT Project in 2019 has strengthened the belief and motivated the researcher to be continued in this domain. This review article aims to provide the complete design flow of hybrid CMOS/MTJ circuits developed using one of the fab compatible MTJ spintronic devices and its integration with conventional CMOS logic. The broad coverage of the article is MTJ construction, its switching mechanisms, a brief history of various compact models, reliability issues, and the concept of logic-in-memory (LIM) architecture. Finally, the article concludes with the challenges and future prospects of hybrid CMOS/MTJ circuits, which will motivate people in academia to cultivate research in this domain and industry to realize the prototype for a wide range of potential applications.

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Tunnel Junction with Perpendicular Magnetic Anisotropy: Status and Challenges

Cited by 47 publications

References 75 publications

Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder

Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder

Tunable Memristic Characteristics Based on Graphene Oxide Charge-Trap Memory

From MTJ Device to Hybrid CMOS/MTJ Circuits: A Review

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