Tunneling field-effect transistor with Si/SiGe material for high current drivability

Abstract

In order to overcome the small current drivability of a tunneling field-effect transistor (TFET), we have introduced a TFET with the SiGe body and elevated Si drain region. The proposed TFET features large on-current and lower subthreshold swing (SS) compared with the Si TFET. Also, by using elevated Si drain region, it is expected that ambipolar current can be suppressed. Through the technology computer aided design (TCAD) simulation, the characteristics of the proposed TFET have been investigated to confirm its superiority in performance. The proposed TFET structure enables self-aligned doping process and has a strong immunity to short-channel effects compared with the conventional TFET. In addition, we have confirmed that both n-and p-channel characteristics can be simultaneously improved by using the proposed TFET.

Core-shell homojunction silicon vertical nanowire tunneling field-effect transistors

“…The measured data45678 show better subthreshold characteristics at high I ds ranges, but mostly-high SS point for the entire I ds range is not promising for low-power applications. Among all the SS point data, both n-type and p-type CS TFETs show the widest I ds range from 10 −16 to 5·10 −10  A/μm under an SS point of 60 mV/dec which is advantageous for higher I on and I on / I off ratio compared to any previously-reported data456789101112. In addition, both n-type and p-type CS TFETs show comparable transfer characteristics and thus are applicable to the CMOS inverter with one-to-one device ratio.…”

“…After the maximum I on / I off ratios within the V DD values are extracted from the transfer curves, the I on values at the maximum I on / I off ratios are obtained. All the simulated data9101112 adopt the default values of A and B for the Kane’s nonlocal BTBT model and thus are comparable to those of the CS TFETs. However, the comparison of DC performance between simulated and measured data is not accurate because the A and B parameters were not adjusted to the measured data beforehand.…”

“…Figure 7 shows the SS point with respect to the I ds of the CS TFETs in this work (red), the measured45678 (black) and the simulated9101112 (blue) silicon homojunction TFETs. The CS TFETs in this work have a D NW of 20 nm, H NW of 400 nm, T shell of 5 nm, T epi of 20 nm, and EOT of 0.8 nm at V ds of 0.5 V. All the measured and simulated I ds are normalized with respect to the device width for planar and to the perimeter for nanowire devices.…”

“…The CS TFETs in this work have a D NW of 20 nm, H NW of 400 nm, T shell of 5 nm, T epi of 20 nm, and EOT of 0.8 nm at V ds of 0.5 V. All the measured and simulated I ds are normalized with respect to the device width for planar and to the perimeter for nanowire devices. The simulated data9101112 show a sub-60-mV/dec of SS point at lower I ds ranges, which makes it difficult to substitute the conventional MOSFETs with respect to device operation speed. The measured data45678 show better subthreshold characteristics at high I ds ranges, but mostly-high SS point for the entire I ds range is not promising for low-power applications.…”

“…Meanwhile, tunneling FETs (TFETs) have been considered as one of the promising alternatives to attain SS below 60 mV/dec and high on/off current ratio under low V DD for mobile applications23456789101112131415. TFETs obey tunneling transport at the source/channel junction by adopting different types of doping between the source and the drain as p-i-n structure.…”