Turn-Around of Threshold Voltage in Gate Bias Stressed p-Channel Power Vertical Double-Diffused Metal–Oxide–Semiconductor Transistors

Davidović, V.; Stojadinović, N.; Danković, Danijel; Golubović, S.; Manić, I.; Djorić-Veljković, S.; Dimitrijev, Sima

doi:10.1143/jjap.47.6272

Cited by 11 publications

(6 citation statements)

References 37 publications

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“…At room temperature, however, significant device degradation can be observed only at stress voltages just a few volts below the gate-oxide breakdown voltage (70 V), and is ascribed to tunneling effects [42]. On the other hand, at temperatures higher than 175 • C, backward interface reactions could be activated [39], so that the bias-temperature combination for NBT stress used in our current study was well selected.…”

Section: Resultsmentioning

confidence: 99%

NBTI and Irradiation Effects in P-Channel Power VDMOS Transistors

Davidović

Danković

Ilić

et al. 2016

IEEE Trans. Nucl. Sci.

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In this paper, we report the results of consecutive irradiation and negative bias temperature (NBT) stress experiments performed on p-channel power vertical double-diffused metal-oxide semiconductor transistors. The purpose is to examine the effects of a specific kind of stress in devices previously subjected to the other kind of stress, as well as to assess if possible the behavior of devices subjected to simultaneous irradiation and NBT stressing. It is shown that irradiation of previously NBT stressed devices leads to a further increase of negative threshold voltage shift due to additional build-up of both oxide trapped charge and interface traps. NBT stress effects in previously irradiated devices may, however, depend on gate bias applied during irradiation and on the total dose received: in the cases of low-dose irradiation or irradiation without gate bias, the subsequent NBT stress seems to lead to further device degradation, whereas in the cases of devices previously irradiated to high doses or with gate bias applied during irradiation, NBT stress seems to have a positive role since it practically anneals a part of radiation-induced degradation.Index Terms-Interface traps, irradiation effects, negative bias temperature instability (NBTI), oxide traps, power devices, thermal annealing, threshold voltage shift, VDMOSFET.

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Section: Resultsmentioning

confidence: 99%

NBTI and Irradiation Effects in P-Channel Power VDMOS Transistors

Davidović

Danković

Ilić

et al. 2016

IEEE Trans. Nucl. Sci.

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show abstract

“…Chosen voltage value of -45 V exceeds the range of gate voltages allowed for application in the investigated devices, but it is within the range of gate voltages used for NBT stress experiments on these power devices. Regarding the choosing of temperature, significant device degradation at room temperature can be observed only at stress voltages which are just few volts below the gate oxide breakdown voltage (70 V), and can be ascribed to tunnelling effects [57], while at T > 175 C, backward interface reactions can be activated [58]. It should be mentioned that in this study the NBT stressing was limited to 168 h with the aim of shortening the experiment.…”

Section: Consecutive Radiation and Nbt Stress Effectsmentioning

confidence: 98%

NBT stress and radiation related degradation and underlying mechanisms in power VDMOSFETs

et al. 2018

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In this paper we provide an overview of instabilities observed in commercial power VDMOSFETs subjected to irradiation, NBT stress, and to consecutive exposure to them. The results have indicated that irradiation of previously NBT stressed devices leads to additional threshold voltage shift, while NBT stress effects in previously irradiated devices depend on the gate bias applied during irradiation and on the total dose received. This points to the importance of the order of applied stresses, indicating that for proper insight into the prediction of device behaviour not only harsh conditions, but also the order of exposure have to be considered. It has also been shown that changes in the densities of oxide trapped charge and interface traps during spontaneous recovery after each of applied stresses can be significant, thus leading to additional instability, even though the threshold voltage seems to remain stable, pointing to the need for clarifying the responsible mechanisms.

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“…As the N channel MOSFETs have a negative threshold voltage shift because of the generation of the positive charges in the oxide traps, however if the interface traps have been created significantly during the bias of the stress, this may convert the direction of the shift. The change of the direction of threshold voltage drift is called the 'turnaround effect' [12]. In this study, the charge trapping process and threshold voltage drift of the commercially available GaN & SiC cascodes will be investigated in the off state of the devices.…”

Section: Introductionmentioning

confidence: 99%

The impact of electrothermal stress on threshold voltage drift of gan and SIC cascode devices

et al. 2022

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Gallium Nitride (GaN) and Silicon Carbide (SiC) power cascode devices both take advantage of a low-voltage enhancementmode Silicon power MOSFET coupled with a high-voltage depletion-mode GaN HEMT or SiC JFET to realize high switching frequencies with the intention of avoiding charge trapping and threshold voltage drift in the gate oxide traps of enhancementmode SiC MOSFETs. Nevertheless, in this paper it is shown that SiC and GaN Cascodes will also suffer from the gate threshold voltage drift when subjected to significant electrothermal stress. This is partly due to the natural drift of threshold voltage in the gate, and partly due to the impact of the leakage current by the high-voltage device. The threshold voltage drift can lead to permanent degradations and potential failures, and as such is the subject of this investigation.

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Turn-Around of Threshold Voltage in Gate Bias Stressed p-Channel Power Vertical Double-Diffused Metal–Oxide–Semiconductor Transistors

Cited by 11 publications

References 37 publications

NBTI and Irradiation Effects in P-Channel Power VDMOS Transistors

NBTI and Irradiation Effects in P-Channel Power VDMOS Transistors

NBT stress and radiation related degradation and underlying mechanisms in power VDMOSFETs

The impact of electrothermal stress on threshold voltage drift of gan and SIC cascode devices

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