Two CMOS time to digital converters using successive approximation register logic

Abstract

This letter presents two CMOS time-to-digital converters (TDCs) with a conventional successive approximation register (SAR) logic and SAR continuous disassembly (CD) logic. In a flash TDC, a high-bit thermometer to binary converter consumes a large silicon area and power, which prevents the simple flash TDC structure be widely used in modern electrical devices. By separating the delay chain in a flash TDC with binary sequences, the SAR logics can eliminate the thermometer to binary code converter essential for a flash TDC. The two TDCs using conventional SAR and SAR CD logics were fabricated in a 0.18 µm CMOS technology with power consumption of 1.5 mW and 1.3 mW at a sampling rate of 10 Msamples/s and occupied 0.074 mm 2 and 0.041 mm 2 active areas, respectively.

A novel TDC/ADC hybrid reconstruction ROIC for LiDAR

“…Also, it's difficult for the LiDAR to identify the secondary return pulse, which is caused by multiple objects, following the primary one. Moreover, the walk time error caused by limited slew rate and response time with comparator can deteriorate the timing accuracy [1,2,3,4]. For the ADC based LiDAR, it can extract more information, including peak and intensity which is relevant to the material and the rate of surface reflectivity of the target objects, from the digitalized full waveforms [5].…”