Two-dimensional arrays of ordered, highly dense and ultra-small Ge nanocrystals on thin SiO<sub>2</sub>layers

Berbézier, Isabelle; Karmous, A.; Ronda, A.; Stoïca, T.; Vescan, L.; Geurt, R; Olzierski, A; Tsoi, E.; Nassiopoulou, A. G.

doi:10.1088/1742-6596/10/1/018

Cited by 8 publications

(4 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This effect has been exploited in order to obtain, at the same time, smaller Ge dots and electrical insulation, in view to the application of these dots as memory cells. The mechanism of Ge islanding on a SiO 2 substrate is different from that on Si because it is basically driven by surface diffusion and equilibrium surface morphology [101]. In this case a Volmer-Weber growth of Ge islands is observed without the formation of a wetting layer, thus allowing a higher dots density [102][103][104][105][106].…”

Section: Flat Sio 2 /Si(001) Substratesmentioning

confidence: 99%

Role of patterning in islands nucleation on semiconductor surfaces

Motta

Szkutnik

Tomellini

et al. 2006

Comptes Rendus. Physique

View full text Add to dashboard Cite

Quantum dots (QDs) grown on semiconductors surfaces are actually the main researchers' interest for applications in the forthcoming nanotechnology era. New frontiers in nanodevice technology rely on the precise positioning of the nucleation site and on controlling the shape and size of the dots. In this article we will review some recent studies regarding the control of the nucleation process on semiconductor surfaces. A few approaches to form ordered patterns on surfaces are described: natural patterning induced by surface instabilities (as step bunching or step meandering), in situ substrate patterning by Scanning Tunneling Microscopy (STM), high resolution patterning by Focused Ion Beam (FIB). Growth of epitaxial layers of semiconductors (Ge/Si(100) and InAs/GaAs(100)) on patterned surfaces has been studied by STM or Atomic Force Microscopy (AFM) unveiling the way in which the first atoms start to aggregate and identifying their exact nucleation site. Control of the dot size to match the patterning typical wavelength has been achieved by using surfactants on misoriented substrates. STM images acquired in real time allows one to identify the mechanism of Ge cluster formation on patterned Si(100), and to follow the island transition from pre-pyramid to pyramid. Nucleation of ordered Ge dots on SiO 2 substrates has been obtained thanks to FIB tight patterning, achieving island densities of 3.5 × 10 10 /cm 2 .

show abstract

Section: Flat Sio 2 /Si(001) Substratesmentioning

confidence: 99%

Role of patterning in islands nucleation on semiconductor surfaces

Motta

Szkutnik

Tomellini

et al. 2006

Comptes Rendus. Physique

View full text Add to dashboard Cite

show abstract

“…While patterned growth of embedded nanocrystals has been realized, only a limited number of techniques have been explored thus far. [7][8][9][10] Here, we demonstrate the patterned growth of ion beam synthesized Si and Ge nanocrystals. Chemical deactivation of the nucleating specie is achieved by coimplantation of oxygen through a lithographically defined mask.…”

Section: Introductionmentioning

confidence: 98%

A Chemical Approach to 3-D Lithographic Patterning of Si and Ge Nanocrystals

Sharp

et al. 2005

MRS Proc.

View full text Add to dashboard Cite

Ion implantation into silica followed by thermal annealing is an established growth method for Si and Ge nanocrystals. We demonstrate that growth of Group IV semiconductor nanocrystals can be suppressed by co-implantation of oxygen prior to annealing. For Si nanocrystals, at low Si/O dose ratios, oxygen co-implantation leads to a reduction of the average nanocrystal size and a blue-shift of the photoluminescence emission energy. For both Si and Ge nanocrystals, at larger Si/O or Ge/O dose ratios, the implanted specie is oxidized and nanocrystals do not form. This chemical deactivation was utilized to achieve patterned growth of Si and Ge nanocrystals. Si was implanted into a thin SiO 2 film on a Si substrate followed by oxygen implantation through an electron beam lithographically defined stencil mask. Thermal annealing of the co-implanted structure yields two-dimensionally patterned growth of Si nanocrystals under the masked regions. We applied a previously developed process to obtain exposed nanocrystals by selective HF etching of the silica matrix to these patterned structures. Atomic force microscopy (AFM) of etched structures revealed that exposed nanocrystals are not laterally displaced from their original positions during the etching process. Therefore, this process provides a means of achieving patterned structures of exposed nanocrystals. The possibilities for scaling this chemical-based lithography process to smaller features and for extending it to 3-D patterning is discussed.

show abstract

“…The production of portable electronic NV memories is very important for the semiconductor industry because of their superiority in the low power consumption, low cost, high memory capacity, and suitable data retention time . As compared with Si, Ge NCs embedded in oxides offer improved charge retention characteristics due to the smaller band gap which provide a higher confinement barrier for retention mode and smaller barrier for program erase modes .…”

Section: Introductionmentioning

confidence: 99%

Non‐volatile memory devices based on Ge nanocrystals

Vasilache

Cismaru

Dragoman

et al. 2015

Physica Status Solidi (a)

View full text Add to dashboard Cite

The article presents the fabrication and characterization of NV (non‐volatile) memory devices based on SiO2/Ge/SiO2 trilayer structures on Si wafers. The trilayer structures were obtained by using the magnetron sputtering method for the deposition of gate SiO2 and intermediate Ge layers and the rapid thermal oxidation for the growth of tunnel SiO2 layer. Rapid thermal annealing was performed for obtaining Ge nanocrystals embedded in the SiO2 gate oxide, as charge‐storage elements. Two NV cross bar memory structures based on two cell sizes of 300 × 300 and 100 × 100 μm2 were manufactured. Capacity–voltage curves were measured on the memory devices, at different frequencies in the 1 kHz–10 MHz range at room temperature (RT) for evidencing the hysteresis loops and for showing that the devices keep memory in time at these frequencies. We have obtained capacity–voltage hysteresis curves with large memory window up to 2 V. We demonstrate that the trilayer structure SiO2/Ge/SiO2/on Si with Ge NCs embedded in the SiO2 gate oxide is suitable for NV memory applications having a large number of cells.

show abstract

Two-dimensional arrays of ordered, highly dense and ultra-small Ge nanocrystals on thin SiO₂layers

Cited by 8 publications

References 11 publications

Role of patterning in islands nucleation on semiconductor surfaces

Role of patterning in islands nucleation on semiconductor surfaces

A Chemical Approach to 3-D Lithographic Patterning of Si and Ge Nanocrystals

Non‐volatile memory devices based on Ge nanocrystals

Contact Info

Product

Resources

About

Two-dimensional arrays of ordered, highly dense and ultra-small Ge nanocrystals on thin SiO2layers

Cited by 8 publications

References 11 publications

Role of patterning in islands nucleation on semiconductor surfaces

Role of patterning in islands nucleation on semiconductor surfaces

A Chemical Approach to 3-D Lithographic Patterning of Si and Ge Nanocrystals

Non‐volatile memory devices based on Ge nanocrystals

Contact Info

Product

Resources

About

Two-dimensional arrays of ordered, highly dense and ultra-small Ge nanocrystals on thin SiO₂layers