Two-dimensional bandgap engineering in a novel Si-SiGe pMOSFET with enhanced device performance and scalability

Ouyang, Q.; Chen, X.D.; Mudanai, S.; Kencke, D.L.; Wang, X.; Tasch, A.F.; Register, Leonard F.; Banerjee, S.

doi:10.1109/sispad.2000.871230

Cited by 3 publications

(2 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The depth of focus of the subsequent gate definition step is where the biggest impact will be realized. Thus the thickness (and control of the thickness) of the SiGe are critical to subsequent processes as well as threshold voltage (11). One possible method of overcoming the NMOS/PMOS offset is with a recess etch prior to SiGe epitaxial growth.…”

Section: Active Area Processingmentioning

confidence: 99%

The Challenges in Introducing PMOS Dual Channel in CMOS Processing

Harris

Majhi²,

Kirsch³

et al. 2009

ECS Trans.

View full text Add to dashboard Cite

The benefit of a SiGe channel in the adjustment of the threshold voltage in PMOS devices is outlined. However, difficulties in the implementation make the full CMOS integration challenging. We examine these difficulties of implementation and the complexities of the processes. The issues are divided into two categories to better understand the complexity: active area related and complementary process related. In particular, the process issues associated with epitaxy, gate etch, silicide and lithography are particularly examined. It is concluded that the issues can be overcome with excellent transistor results.

show abstract

Section: Active Area Processingmentioning

confidence: 99%

The Challenges in Introducing PMOS Dual Channel in CMOS Processing

Harris

Majhi²,

Kirsch³

et al. 2009

ECS Trans.

View full text Add to dashboard Cite

show abstract

“…For the band-gap engineering in the device structure, a high-performance modulationdoped FET (MODFET) has been demonstrated by using a p-type strained SiGe channel [3]. The band offset in a heterojunction MOSFET (HJMOSFET) with a strained SiGe source/drain has been also found to be able to substantially suppress the short-channel effect, drain-induced barrier lowering (DIBL) effect, and punchthrough [4]. Moreover, an n-channel-SiGe flash-memory device has been proposed to enhance the channel-initiated-secondary-electron (CHISEL) injection by band-edge offsets and band-gap reduction [5], [6].…”

Section: Introductionmentioning

confidence: 99%

Enhanced Band-to-Band-Tunneling-Induced Hot-Electron Injection in p-Channel Flash by Band-gap Offset Modification

Wang

Chang‐Liao

et al. 2006

IEEE Electron Device Lett.

View full text Add to dashboard Cite

A novel p-channel flash device with a SiGe layer is proposed, which is based on the analysis made with the simulator MEDICI, to enhance the band-to-band-tunneling current and improve the programming speed. The programming biases of the p-channel flash device can be reduced with an equal programming speed. Simulation results show that more than one hundred times enhancement in the programming speed or 35% reduction of the drain voltage can be achieved in the proposed p-channel flash device with a 40% Ge content in the surface SiGe layer. In addition, a Si-cap layer is inserted between the SiGe and the tunneling oxide to obtain a high-quality interface and to optimize the cell structure.Index Terms-Band-to-band-tunneling-induced hot-electron (BBHE), high programming speed, low-voltage operation, p-channel flash, SiGe.

show abstract