Two-Dimensional Flex Sensor Exploiting Stacked Ultrathin Chips

Endler, Stefan; Ferwana, Saleh; Rempp, Horst; Harendt, Christine; Burghartz, Joachim N.

doi:10.1109/led.2011.2178389

Cited by 16 publications

(5 citation statements)

References 6 publications

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“…Instead of a dummy chip a second active CMOS chip could be stacked on top of the first CMOS die. If those two stacked CMOS chips are interconnected by means of through silicon vias at the top die, a HySiF microsystem with a stress-sensitive top layer for stress sensing functions and a stress compensated bottom layer for stress-insensitive signal processing purposes can be built [45].…”

Section: A Leveraging the Neural Line Of Stressmentioning

confidence: 99%

Hybrid Systems-in-Foil—Combining the Merits of Thin Chips and of Large-Area Electronics

Burghartz

Alavi

Albrecht

et al. 2019

IEEE J. Electron Devices Soc.

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This paper reports on the status of a comprehensive ten-year research and development effort toward hybrid system-in-foil (HySiF). In HySiF, the merits of high-performance integrated circuits on ultra-thin chips and of large-area and discrete electronic component implementation are combined in a complementary fashion in and on a flexible carrier substrate. HySiF paves the way to entirely new applications of electronic products where form factor, form adaptivity and form flexibility are key enablers. In this review paper the various aspects of thin-chip fabrication and embedding, device and circuit design under impact of unknown or variable mechanical stress, and the on-and off-chip implementation of sensor, actuator, microwave, and energy supply components are addressed. INDEX TERMS Hybrid integrated circuits, thin film circuits, flexible electronics, micro assembly, multichip modules, chip scale packaging.

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Section: A Leveraging the Neural Line Of Stressmentioning

confidence: 99%

Hybrid Systems-in-Foil—Combining the Merits of Thin Chips and of Large-Area Electronics

Burghartz

Alavi

Albrecht

et al. 2019

IEEE J. Electron Devices Soc.

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“…The thickness and stiffness of each layer influences the resulting stress in the silicon chip. By changing one of the glue layers alone, it is possible to considerably change the stress range [22]. Therefore, a calibration is required each time the stack is changed.…”

Section: Digital Controllermentioning

confidence: 99%

An Ultra-Thin Flexible CMOS Stress Sensor Demonstrated on an Adaptive Robotic Gripper

Mahsereci

Saller

Richter

et al. 2016

IEEE J. Solid-State Circuits

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An ultra-thin (20 µm), flexible CMOS stress sensor for hybrid systems-in-foil (HySiF) is presented. The system is designed for Fin Ray ® grippers in order to measure the emerging stress on the gripper in operation, enabling the extraction of object shape and operation status. In-plane stress is linearly converted to electrical signals proportional to shear stress and normal stress difference using two sensing elements. Each stress signal is processed and digitized by an integrator and a 10-bit SAR ADC. In contrast to rigid chips, the stress cannot be avoided in the sensitive blocks, such as the signal processing chain and digital controller, when an ultra-thin chip is under deformation. The influence of stress levels, up to 350 MPa, is minimized by using stress-insensitive components, design measures, and layout techniques. This work represents the first demonstration of stress-aware top-to-bottom CMOS design on an ultra-thin chip.

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“…Stacking of two active chips may not only allow for stress compensation on the lower signal processing die (Fig. 3) and stress maximization on the upper stress sensing die, but will also provide means of eliminating temperature effects on both dies [10].…”

Section: Integrated Stress Sensors and Stress Compensationmentioning

confidence: 99%