Two dimensional modeling of dual material double gate TFET in stacked hetero-dielectrics with split high-K materials

Das, Dipshika; Ghosh, Pradip; Dhar, Rudra Sankar

doi:10.1109/edkcon56221.2022.10032942

Cited by 1 publication

(1 citation statement)

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“…Nonetheless, the devices developed so far are not able provide the required performance. Hence to achieve high I ON /I OFF ratio, lower subthreshold slope, and minimal leakages current (I OFF ), a novel approach has been implemented [22] here and a comparison among various gate oxide architectures have been furnished for further improvement of the electrical characteristics. An outline of analytical model for the proposed structures has been given here to derive and calculate the threshold voltage for the device, thereby employed for validating the device design.…”

Section: Introductionmentioning

confidence: 99%

Performance evaluation of split high–K material based stacked hetero-dielectrics tunnel FET

Das,

Dhar,

Ghosh

2023

Phys. Scr.

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This research investigates the performance evaluation of a double gate TFET (DGTFET) by employing a hetero-dielectric gate structure featuring distinct high-K dielectrics with different work functions in a dual-material gate configuration. The gate dielectric stack is comprised of split high–K materials placed on the SiO2 dielectric. An outline of the analytical model for the validation of the novel device is developed and 2-D simulations-based analysis and investigation are carried out. The impact of different high-K dielectric materials layered on top of silicon dioxide (SiO2) is examined; its effect on transfer characteristics, subthreshold swing (SS), minimum tunneling width, ratio of ON to OFF currents ION/IOFF, and energy band bending are investigated. The work functions optimization for the auxiliary and tunnel gates are made in this work to minimize OFF current, to reduce ambipolar phenomena and to enhance tunnel rate. The effects of gate potentials, source/ drain doping concentrations on the results are further studied. The threshold voltage of DGTFET is also modelled and computed for the proposed structures. The present findings revealed that the low OFF current (10-17 A/µm) is provided by the proposed device structure, improved ratio of ION/IOFF (1011), and lowered subthreshold swing required for future era.

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Section: Introductionmentioning

confidence: 99%