Two-dimensional signal gating for low-power array multiplier design

In this paper a new method is proposed to reduce power and area of the array multiplier. In the proposed method vector merging final adder is removed at final stage of the multiplier, at the final stage the generated carry is given to the input of the column of top adder. The adders also do the same what the vector merging final adder can do. The method is applied for array multiplier and column bypassing multiplier (CBM). The results are carried out by H-Spice with different TSMC (Standard and PTM) technology files at a supply voltage 2.0V. Array multiplier has shown 13.91% and Proposed Column Bypassing Multiplier (PCBM) shown 23.38% less power consumption for 180nm CMOS technology than the conventional array multiplier and CBM. 14-T full adder is used to design the multipliers. Due to elimination of the final adder proposed method saves 56 transistors and cause low area. Embedded, DSP General Terms

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“…ripple carry or carry-look ahead) adder stage. This is the conventional array multiplier with CSA similar to - Figure (2)‖ [6].…”

Section: Array Multipliermentioning

confidence: 99%

Performance Evaluation of Bypassing Array Multiplier with Optimized Design

Ravi¹,

Dr.T.S.Rao²,

Dr.T.J.Prasad³

2011

IJCA

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“…Though many efforts have been focused on the improvement of multiplier designs [1,3,4,6,7] to challenge the high speed circuit is the high power consumption, which is not a tolerable price to pay in recent mobile technologies. Digital multipliers are the most critical arithmetic functional unit in many DSP applications, e.g., Fourier Transform, DCT, filtering, etc., Array and parallel multipliers are very welcomed due to their high execution speed and throughput.…”

Section: Introductionmentioning

confidence: 99%

“…Many prior techniques were aimed at transition or switch reductions to reduce power dissipation. A 2-dimensional signal gating method for low power array multiplier design [1] approach provides gating lines for both multiplicand and multiplier operands. By deactivated different regions in the multiplier, power dissipation could be reduced by reducing unwanted transitions.…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of Power Aware FIR Filter Using Reduced Transition Pipelined Variable Precision Gating

Senthilkumar¹,

Natarajan²

2008

J. of Computer Science

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With the emergence of portable computing and communication system, power awareness is one of the major objectives of VLSI Design. This is its ability to scale power consumption based on the time-varying nature of inputs. Even though the system is not designed for being power aware, systems display variations in power consumption as conditions change. This implies, by the definition above, that all systems are naturally power aware to some extent. However, one would expect that some systems are more power aware than others. Equivalently, the system should be able to re designed to increase their power awareness. This research proposes a pipelined Variable precision gating scheme to improve the power awareness of the system. This research illustrates this technique by applying it to FPGA Implementation of multipliers and digital FIR filters. This proposed technique is to clock gating to registers in both data flow direction and vertical to data flow direction within the individual pipeline stage based on the input data precision. For signed multipliers using 2's complement representation, sign extension, which wastes power and causes longer delay, could be avoided by implementing this technique. Very little additional area is needed for this technique. The designed circuit is simulated, synthesized and implemented in Xilinx Spartan 3e FPGA. The Power is analyzed for the designed circuit and the power saving of 18 % obtained for the proposed FIR Filter with 3 % increase in area compared to the existing pipeline gating design

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“…We used the Baugh-Wooley algorithm [8] to investigate the impact of the twin-precision feature on delay and power of a signed tree multiplier 4 . Here, signed multiplication is performed by first inverting all partial product bits that are results of the most significant bit (MSB) of exactly one of the operands, Figure 3.…”

Section: Signed Multiplication According To Baughwooleymentioning

confidence: 99%

“…It has been shown [4] that it is relatively straightforward to partition an array multiplier, so as to obtain a multiplier that can perform multiplications with varying operand size 1 . In comparison to tree multipliers, however, an array multiplier is slow and power hungry which makes it a poor design choice when a fast and efficient multiplier is needed [5].…”

Section: Introductionmentioning

confidence: 99%