Two Elementary Instructions Make Compare-and-Swap

Khanchandani, Pankaj; Wattenhofer, Roger

doi:10.1109/ipdps.2019.00046

Cited by 2 publications

(1 citation statement)

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“…Though efficient, this has been shown to induce significant issues, which requires a new LL/SC emulation scheme [1]. Research has also investigated improving upon the implementation of CAS [5].…”

Section: Related Work a Implementation And Optimizationmentioning

confidence: 99%

Implementing and Breaking Load-Link / Store-Conditional on an ARM-Based System

Tilley¹,

Liebeskind²,

Asensio³

2022

Preprint

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Manufacturers of modern electronic devices are constantly attempting to implement additional features into ever-increasingly complex and performance demanding systems. This race has been historically driven by improvements in the processor's clock speed, but as power consumption and real estate concerns in the embedded space pose an growing challenge, multithreading approaches have become more prevalent and relied upon. Synchronization is essential to multithreading systems, as it ensures that threads do not interfere with each others' operations and produce reliable and consistent outputs whilst maximizing performance and efficiency. One of the primary mechanisms guaranteeing synchronization in RISC architectures is the load-link/store conditional routine, which implements an atomic operation that allows a thread to obtain a lock. In this study, we implement, test, and manipulate an LL/SC routine in a multithreading environment using GDB. After examining the routine mechanics, we propose a concise implementation in ARMv7l, as well as demonstrate the importance of register integrity and vulnerabilities that occur when integrity is violated under a limited threat model. This work sheds light on LL/SC operations and related lock routines used for multithreading.

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Section: Related Work a Implementation And Optimizationmentioning

confidence: 99%