Two-Stage Multi-bit Flip-Flop Clustering with Useful Skew for Low Power

Kao, Hsu-Yu; Hsu, Chu-Han; Huang, Shih-Hsu

doi:10.1109/iccet.2019.8726883

Cited by 3 publications

(1 citation statement)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Flip-flops (FFs) are usually used in digital systems to store data. To reduce the clock power, several FFs can be grouped into a module called a multibit FF (MBFF), replacing several flip-flops [18]. Each flip-flop contains two inverters which generate opposite-phase clock signals.…”

Section: Power Optimization By Mbff Techniquementioning

confidence: 99%

Design of Low-Power Structural FIR Filter Using Data-Driven Clock Gating and Multibit Flip-Flops

Touil

Hamdi

Gassoumi

et al. 2020

Journal of Electrical and Computer Engineering

View full text Add to dashboard Cite

Optimization for power is one of the most important design objectives in modern digital signal processing (DSP) applications. The digital finite duration impulse response (FIR) filter is considered to be one of the most essential components of DSP, and consequently a number of extensive works had been carried out by researchers on the power optimization of the filters. Data-driven clock gating (DDCG) and multibit flip-flops (MBFFs) are two low-power design methods that are used and often treated separately. The combination of these methods into a single algorithm enables further power saving of the FIR filter. The experimental results show that the proposed FIR filter achieves 25% and 22% power consumption reduction compared to that using the conventional design.

show abstract

Section: Power Optimization By Mbff Techniquementioning

confidence: 99%