UART Receiver Synchronization: Investigating the Maximum Tolerable Clock Frequency Deviation

Raj, Mitu

doi:10.17485/ijst/2017/v10i25/115278

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2019

2024

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Serial communication protocol for FPGA-based systems

Ivanov

Nosov

2019

J. Phys.: Conf. Ser.

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The article presents results of development of communication protocol for UART-like FPGA-systems. Developed communication protocol supports asynchronous oversampled signal transmission, with 4b/6b encoding for DC-balance maintaining. Algorithm of CPLD-based receiver of signals forming by this protocol is described. This development is relevant for the task of continuous transmission of several control signals over a fiber-optic line, when the use of ready-made UART devices is unjustified. The presented protocol and algorithm are easily implemented on the FPGA and can be used in devices where it is important to minimize the number of elements used. Also, the protocol contains encoding that allows the transmission of low-frequency signals along a line with DC-coupling.

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