UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations

Kulkarni, R. N.; Kim, Jusung; Jeon, Hyung-Joon; Xiao, Jie; Silva-Martí­nez, J.

doi:10.1109/tvlsi.2010.2096438

Cited by 19 publications

(6 citation statements)

References 28 publications

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“…Most relevant work focuses on the former one with an emphasis on class AB transconductors. Nonetheless, class-AB transconductors are inherently power-hungry and possess a medium noise figure [10]. In addition, its common mode feedforward and feedback circuitry needs special care in common mode analysis, and its layout and routing are complex [6,13].…”

Section: Programmable G M -C Lpfmentioning

confidence: 99%

“…The authors of [9] proposed a fourth-order merged closed-loop analog baseband topology, which integrates the channel selection and gain programmability in one merged PGA/LPF biquad. However, the closed-loop topology is intrinsically power-hungry and frequency limited since the operational amplifier should exhibit gain bandwidth product (GBW) several times larger than closed-loop bandwidth requirement [10,11]. Therefore, there is no unique optimum solution, but a myriad solution with a variety proportional to the number of input specifications, with the expectation of sufficiently fine gain resolution, bandwidth programmability, excellent noise/linearity performance, acceptable chip footprint and low power consumption.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Reconfigurable Analog Baseband Circuitry for LFMCW RADAR Receivers in 130-nm SiGe BiCMOS Process

et al. 2020

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A highly reconfigurable open-loop analog baseband circuitry with programmable gain, bandwidth and filter order are proposed for integrated linear frequency modulated continuous wave (LFMCW) radar receivers in this paper. This analog baseband chain allocates noise, gain and channel selection specifications to different stages, for the sake of noise and linearity tradeoffs, by introducing a multi-stage open-loop cascaded amplifier/filter topology. The topology includes a course gain tuning pre-amplifier, a folded Gilbert variable gain amplifier (VGA) with a symmetrical dB-linear voltage generator and a 10-bit R-2R DAC for fine gain tuning, a level shifter, a programmable Gm-C low pass filter, a DC offset cancellation circuit, two fixed gain amplifiers with bandwidth extension and a novel buffer amplifier with active peaking for testing purposes. The noise figure is reduced with the help of a low noise pre-amplifier stage, while the linearity is enhanced with a power-efficient buffer and a novel high linearity Gm-C filter. Specifically, the Gm-C filter improves its linearity specification with no increase in power consumption, thanks to an alteration of the trans-conductor/capacitor connection style, instead of pursuing high linearity but power-hungry class-AB trans-conductors. In addition, the logarithmic bandwidth tuning technique is adopted for capacitor array size minimization. The linear-in-dB and DAC gain control topology facilitates the analog baseband gain tuning accuracy and stability, which also provides an efficient access to digital baseband automatic gain control. The analog baseband chip is fabricated using 130-nm SiGe BiCMOS technology. With a power consumption of 5.9~8.8 mW, the implemented circuit achieves a tunable gain range of −30~27 dB (DAC linear gain step guaranteed), a programmable −3 dB bandwidth of 18/19/20/21/22/23/24/25 MHz, a filter order of 3/6 and a gain resolution of better than 0.07 dB.

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Section: Programmable G M -C Lpfmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Reconfigurable Analog Baseband Circuitry for LFMCW RADAR Receivers in 130-nm SiGe BiCMOS Process

et al. 2020

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“…Figure shows the I‐channel architecture of the analog receiving baseband filter, which comprises a fully differential low‐pass filter, 2‐stage programmable gain amplifier (PGA), and DCOC mechanism. The first stage of the receiving chain is the seventh Chebyshev low‐pass filter with leap‐frog structure to alleviate process, voltage, and temperature (PVT) variations and to increase the overall stability.…”

Section: Each Block Of Analog Baseband Filtermentioning

confidence: 99%

A programmable analog baseband filter with DC offset reduction using servo loop feedback

Chang

2018

Circuit Theory & Apps

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Summary This paper presents a programmable analog baseband filter with direct current (DC) offset cancelling, using the standard complementary metal‐oxide‐semiconductor process. The servo loop feedback topology is adopted to reject in‐band DC offset at each stage of the receiving system. Furthermore, the proposed back‐to‐back diode‐connected configuration forms an ultrahigh pseudo resistor, which is applied in the feedback path of the integrator to obtain an ultralow cut‐off frequency (<1 Hz) for the high‐pass response. Therefore, low‐frequency application is possible for simultaneously in‐band DC offset and out‐band interference suppression. A servo loop feedback system with a pseudo resistor is used in the analog baseband filter to verify the concept. The chip is fabricated by using the TSMC 0.13‐um complementary metal‐oxide‐semiconductor process and consumes 43.8 mA from a 1.2 V DC supply voltage. The measured gain variation is from 65.6 to −3.3 dB with a resolution of 1 dB at a bandwidth of 5 MHz. The bandwidth is adjustable from 1.75 to 10 MHz.

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“…Therefore, great efforts have been made to maximize the dynamic range of a certain system. Although gain tuning technique has been implemented with various building blocks, such as low noise amplifier (LNA) [3], power amplifier (PA) [4], trans-impedance amplifier (TIA) [5], [6], etc., incorporating variable gain amplifier (VGA) is still the most efficient way to boost the dynamic range. Based on the control methods, two categories of VGAs are well adopted in the communication systems, namely, digitally-controlled VGA and analog-controlled VGA.…”

Section: Introductionmentioning

confidence: 99%

Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique

Kong

Chen

et al. 2021

IEEE Access

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This paper reports two variable-gain amplifiers (VGAs) featuring a new pseudo-currentsteering gain-tuning technique. In the first VGA (VGA-I), a single-voltage-controlled dual-branch current mirror is developed as a standalone gain control block. In the second VGA (VGA-II), two NMOS transistors, which are biased by a tunable voltage, are integrated into a conventional common-source amplifier to steer away from a part of the total current. Meanwhile, the theoretical analysis is developed to reveal the mechanism of different gain tuning. Fabricated in a 40-nm CMOS process, VGA-I (VGA-II) occupies a tiny area of 0.03 mm 2 (0.024 mm 2) and consumes 22 mW (20 mW). Measured over a gain range of > 64 dB, the-3-dB bandwidth of VGA-I (VGA-II) is 9 GHz (6.6 GHz). For the time-domain tests, VGA-I (VGA-II) exhibits a jitter of 40 ps (30 ps), under a 2 7-1 PRBS input at 12 Gb/s. Their power efficiencies (1.83 and 1.67 pJ/bit) compare favorably with state-of-the-art. INDEX TERMS CMOS, high-speed transceiver, variable-gain amplifier (VGA), negative capacitance (NC), peak-to-peak jitter, data-dependent jitter (DDJ), pseudo-current steering, wide-tuning gain control, dual-branch current mirror, active inductor.

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UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations

Cited by 19 publications

References 28 publications

A Reconfigurable Analog Baseband Circuitry for LFMCW RADAR Receivers in 130-nm SiGe BiCMOS Process

A Reconfigurable Analog Baseband Circuitry for LFMCW RADAR Receivers in 130-nm SiGe BiCMOS Process

A programmable analog baseband filter with DC offset reduction using servo loop feedback

Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique

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