Ultra‐energy‐efficient temperature‐stable physical unclonable function in 65 nm CMOS

Abstract

An Ultra-Energy-Efficient Temperature-Stable Physical Unclonable Function in 65nm CMOS. Electronics LettersAccess to the published version may require subscription. N.B. When citing this work, cite the original published paper. Permanent link to this version:http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-183776An Ultra-Energy-Efficient Temperature-Stable Physical Unclonable Function in 65nm CMOS S. Tao and E. Dubrova Physical unclonable functions (PUFs) are promising hardware security primitives suitable for resource-constrained devices requiring lightweight cryptographic methods. This letter proposes an ultra-lowpower and reliable PUF based on a customized dynamic two-stage comparator operating in the sub-threshold region. The proposed PUF is implemented in a standard 65nm CMOS technology and validated through Monte-Carlo simulations. Evaluation results show a worst-case reliability of 98.3% over the commercial temperature range of 0• C to 85• C and 10% fluctuations in supply voltage. In addition, the 128-bit PUF array consumes only 1.33 µW at 1 Mb/s, which corresponds to 10.3 fJ/bit, being the most energy-efficient design to date.Introduction: Physical unclonable functions (PUFs) make use of the inherent process variation in physical devices to generate unique chip IDs or secure keys. For reliable identification/authentication, PUFs should be robust against varying operating environment conditions. Moreover, silicon PUFs are usually integrated into radio-frequency identification (RFID) tags and smart card ICs [1], which are powered by battery or even harvested energy. Therefore, the circuit implementation of these PUFs must be highly energy-efficient.Silicon PUFs developed up to now, either delay based (e.g., ring oscillator-and arbiter-PUFs) or memory based (e.g., SRAM-PUFs), mostly employ standard logic cells for circuit implementation. These conventional PUF designs have no flexibility to size the transistors for power/performance optimisation. In addition, they are generally very sensitive to environmental variations resulting in significantly increased errors in response bits. To improve the reliability, a few customized PUF implementations have been reported [2,3], which rely on analogue/static circuit blocks. In this work, we take a step further by proposing a PUF design that does not only show sufficient uniqueness and reliability, but also achieves excellent energy-efficiency.

A highly reliable butterfly PUF in SRAM-based FPGAs

“…Physically unclonable function (PUF) [1,2,3], an innovative hardware security technology, exploits physical randomness derived from uncontrollable integrated circuit (IC) manufacturing process [4] to generate high-security secret keys. Good randomness in PUF outputs comes from highly symmetrical placement and isometric routing [5], i.e., no systematic skews in the circuit implementation, only in this way can the minute and random mismatches induced by manufacturing process dominate the PUF outputs.…”

The effect of power supply ramp time on SRAM PUFs

“…In other words, Reliability of a PUF measures its ability to produce the same responses under varying environmental conditions, e.g. temperature and supply voltage [7]. It is also accessed by the Hamming Distance (HD).…”

“…Randomness (intra-chip randomness) is a measure of the unpredictability of the response [7]. This implies (i) unpredictability of a response for a new challenge despite the prior knowledge of a large number of challenge-response pairs (CRPs) as well as (ii) unpredictability of every bit in the response even with a knowledge of all other response bits [8].…”

Chaos-Based Physical Unclonable Functions

“…The advantages and applications of PUFs initiated a search for methods of harvesting of PUF keys from physical processes. Among proposed solutions, we can find: ring oscillators [7,9], transient effect ring oscillators [10], dynamic ring oscillators [11], ordering-based ring oscillator [12], convergence time of bistable rings [8], sneak paths in the resistive X-point array [13], power consumption differences of Advanced Encryption Standard Sbox inversion functions [14], occurrence of metastability [15], static memory [16,17], dynamic memory [18,19], switching behavior of emerging magneto-resistive memory devices [20], switching of resistive random access memory [21], reduction-oxidation resistive switching memories [22], decay-based Dynamic Random Access Memory [23], locally enhanced defectivity [24], combination of multiplexers and arbiters [25], wireless sensors [26], Complementary Metal-Oxide Semiconductor image sensors [27], nonlinearities of data converters [28], mismatch of capacitor ratios [29], primitive shifting permutation network (barrel shifter) [30], cellular neural networks [31], customized dynamic two-stage comparator [32], and many others.…”