Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs

Peluso, Valentino; Calimera, Andrea; Macii, Enrico; Aliotoy, Massimo

doi:10.1109/vlsi-soc.2016.7753580

Cited by 5 publications

(2 citation statements)

References 15 publications

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“…Then, due to the advancement in process technologies and the emergence of design technologies such as power gating, voltage islands, and fine-grained dynamic voltage frequency scaling [18]- [20], timing variability due to process, voltage, and temperature variations became critical to the timing closure efficiency of logic circuits. The industry adopted multicorner multi-mode (MCMM) timing analysis and transitioned from the derating to performing sign-off at every operating condition.…”

Section: B Corner Explosion and Timing Closurementioning

confidence: 99%

Cross-Corner Delay Variation Model for Standard Cell Libraries

Kim

Joo²,

Park

et al. 2021

IEEE Access

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For timing closure of logic circuits, circuit designers must perform sign-offs on a variety of process, voltage, and temperature (PVT) conditions. Designs of advanced logic circuits involve a multitude of voltage islands and operating modes, each of which requires delay characterizations at nearby PVT corners. Furthermore, advanced technologies nodes suffer from corner explosion: while the impact of PVT variations is being exacerbated, process variations are also diversifying, increasing the number of operating conditions exponentially. This paper revisits the importance of cross-corner timing estimations and proposes a delay variation model to mitigate such corner explosion. Our objective is to reduce PVT corner characterization effort for timely static timing analysis on an exploding number of operating conditions. Our proposed Decomposed Propagation Vector Variation Model (DPVVM) decomposes propagation delay and timing constraints into the driving by the receiver cell and its driver cell; by scaling them separately, delay characterization effort is reduced to a fraction of time while realizing accurate timing estimations. We also propose Multi-Dimension Recomposition (MDR) scheme, which exploits a multitude of pre-characterized corners to further improve the consistency of cross-corner timing estimations. As a result, with only 8.0% of a corner characterization effort compared to the full-characterization, DPVVM combined with MDR achieves overall cross-corner timing estimation errors of 4.8% and 5.6% for single cells and complex logic circuits-or improvements of 69% and 61% over the conventional derating method, respectively. Our proposed method's characterization overhead is 11% over the conventional derating method; the overhead is marginal, accounting for only 0.76% of a full-characterization time.

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Section: B Corner Explosion and Timing Closurementioning

confidence: 99%

Cross-Corner Delay Variation Model for Standard Cell Libraries

Kim

Joo²,

Park

et al. 2021

IEEE Access

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“…While the aforementioned techniques aim at pushing power consumption close to ideal-DVFS, this work proposes a solution that goes beyond that theoretical limit. Recalling the practical implementation described in [9], in this work we give a comprehensive parametric analysis of the main advantages brought by a Vdd-Hopping scheme applied at a ultra-fine granularity, i.e., within-the-core. Such a solution, called FINE-VH, represents a viable solution to achieve power consumption below ideal-DVFS by using a dual-Vdd scheme.…”

Section: Introductionmentioning

confidence: 99%

Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping

Peluso

Rizzo

Calimera

et al. 2017

IFIP Advances in Information and Communication Technology

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DVFS is the de-facto standard for low energy Multi-Processor SoCs. It is based on the simple, yet efficient principle of lowering the supply voltage (Vdd) to the minimum threshold that satisfies the frequency constraint (f clk) required by the actual workload. An ideal-DVFS deals with the availability of on-chip high resolution voltage regulators that can deliver the supply voltage with a fine step resolution, a design option that is too costly. While previous research focused on alternative solutions that can achieve, or at least get close to, the efficiency of ideal-DVFS while using a discrete set of supply voltages, this work introduces Ultra-Fine Grain Vdd-Hopping (FINE-VH), a practical methodology that brings DVFS beyond its theoretical limit. FINE-VH leverages the working principle of Vdd-Hopping applied withinthe-core by means of a layout-assisted, level-shifter free, dynamic dual-Vdd control strategy in which leakage currents are minimized through an optimal timing-driven poly-bias assignment procedure. We propose a dedicated back-end flow that guarantees design convergence with minimum area/delay overhead for a cutting-edge industrial Fully-Depleted SOI (FDSOI) CMOS technology at 28 nm. Experimental results demonstrate FINE-VH allows substantial power savings w.r.t. coarse-grain (i) ideal-DVFS, (ii) Vdd-Hopping, (iii) Vdd-Dithering, when applied on the design of a RISC-V architecture. A quantitative analysis provides an accurate assessment of both savings and overheads while exploring different design options and different voltage settings.

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